982cfa2f0e
This patch fixes max loop count in EQ(Channel Equalization) sequence of link training. According to DP(displayport) specification, the max loop count in this sequence should be 5. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
131 lines
2 KiB
C
131 lines
2 KiB
C
/*
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* Samsung SoC DP device support
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _EXYNOS_DP_H
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#define _EXYNOS_DP_H
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#define DP_TIMEOUT_LOOP_COUNT 100
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#define MAX_CR_LOOP 5
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#define MAX_EQ_LOOP 5
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enum link_rate_type {
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LINK_RATE_1_62GBPS = 0x06,
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LINK_RATE_2_70GBPS = 0x0a
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};
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enum link_lane_count_type {
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LANE_COUNT1 = 1,
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LANE_COUNT2 = 2,
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LANE_COUNT4 = 4
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};
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enum link_training_state {
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START,
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CLOCK_RECOVERY,
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EQUALIZER_TRAINING,
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FINISHED,
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FAILED
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};
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enum voltage_swing_level {
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VOLTAGE_LEVEL_0,
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VOLTAGE_LEVEL_1,
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VOLTAGE_LEVEL_2,
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VOLTAGE_LEVEL_3,
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};
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enum pre_emphasis_level {
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PRE_EMPHASIS_LEVEL_0,
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PRE_EMPHASIS_LEVEL_1,
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PRE_EMPHASIS_LEVEL_2,
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PRE_EMPHASIS_LEVEL_3,
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};
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enum pattern_set {
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PRBS7,
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D10_2,
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TRAINING_PTN1,
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TRAINING_PTN2,
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DP_NONE
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};
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enum color_space {
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COLOR_RGB,
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COLOR_YCBCR422,
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COLOR_YCBCR444
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};
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enum color_depth {
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COLOR_6,
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COLOR_8,
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COLOR_10,
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COLOR_12
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};
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enum color_coefficient {
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COLOR_YCBCR601,
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COLOR_YCBCR709
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};
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enum dynamic_range {
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VESA,
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CEA
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};
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enum pll_status {
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PLL_UNLOCKED,
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PLL_LOCKED
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};
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enum clock_recovery_m_value_type {
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CALCULATED_M,
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REGISTER_M
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};
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enum video_timing_recognition_type {
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VIDEO_TIMING_FROM_CAPTURE,
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VIDEO_TIMING_FROM_REGISTER
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};
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enum analog_power_block {
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AUX_BLOCK,
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CH0_BLOCK,
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CH1_BLOCK,
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CH2_BLOCK,
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CH3_BLOCK,
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ANALOG_TOTAL,
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POWER_ALL
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};
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struct video_info {
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char *name;
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bool h_sync_polarity;
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bool v_sync_polarity;
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bool interlaced;
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enum color_space color_space;
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enum dynamic_range dynamic_range;
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enum color_coefficient ycbcr_coeff;
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enum color_depth color_depth;
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enum link_rate_type link_rate;
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enum link_lane_count_type lane_count;
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};
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struct exynos_dp_platdata {
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struct video_info *video_info;
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void (*phy_init)(void);
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void (*phy_exit)(void);
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};
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#endif /* _EXYNOS_DP_H */
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