Florian Fainelli 4348f7e2ae FPGA: Add TS-7300 FPGA manager ... Add support for loading bitstreams on the Altera Cyclone II FPGA populated on the TS-7300 board. This is done through the configuration and data registers offered through a memory interface between the EP93xx SoC and the FPGA via an intermediate CPLD device. The EP93xx SoC on the TS-7300 does not have direct means of configuring the on-board FPGA other than by using the special memory mapped interface to the CPLD. No other entity on the system can control the FPGA bitstream. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Alan Tull <atull@opensource.altera.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-03-17 15:10:48 +09:00
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altera-fpga2sdram.c	ARM: socfpga: checking the wrong variable	2016-11-17 08:14:55 +01:00
altera-freeze-bridge.c	fpga: add altera freeze bridge support	2016-11-10 17:03:36 +01:00
altera-hps2fpga.c	ARM: socfpga: fpga bridge driver support	2016-11-10 17:03:36 +01:00
fpga-bridge.c	fpga: fix sparse warnings in fpga-mgr and fpga-bridge	2017-03-17 15:10:48 +09:00
fpga-mgr.c	fpga: fix sparse warnings in fpga-mgr and fpga-bridge	2017-03-17 15:10:48 +09:00
fpga-region.c	fpga: region: Add fpga-region property 'encrypted-fpga-config'	2017-03-17 15:10:48 +09:00
Kconfig	FPGA: Add TS-7300 FPGA manager	2017-03-17 15:10:48 +09:00
Makefile	FPGA: Add TS-7300 FPGA manager	2017-03-17 15:10:48 +09:00
socfpga-a10.c	fpga: Clarify how write_init works streaming modes	2016-11-29 15:51:49 -06:00
socfpga.c	fpga-mgr: add fpga image information struct	2016-11-10 17:03:35 +01:00
ts73xx-fpga.c	FPGA: Add TS-7300 FPGA manager	2017-03-17 15:10:48 +09:00
zynq-fpga.c	fpga: zynq: Add support for encrypted bitstreams	2017-03-17 15:10:48 +09:00