2c6e759990
Usual iomem annotations + NULL noise removal. Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
289 lines
7.9 KiB
C
289 lines
7.9 KiB
C
/*
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* drivers/serial/mpsc.h
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __MPSC_H__
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#define __MPSC_H__
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/mv643xx.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#define MPSC_NUM_CTLRS 2
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/*
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* Descriptors and buffers must be cache line aligned.
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* Buffers lengths must be multiple of cache line size.
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* Number of Tx & Rx descriptors must be powers of 2.
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*/
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#define MPSC_RXR_ENTRIES 32
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#define MPSC_RXRE_SIZE dma_get_cache_alignment()
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#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
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#define MPSC_RXBE_SIZE dma_get_cache_alignment()
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#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
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#define MPSC_TXR_ENTRIES 32
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#define MPSC_TXRE_SIZE dma_get_cache_alignment()
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#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
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#define MPSC_TXBE_SIZE dma_get_cache_alignment()
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#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
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#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
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MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
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dma_get_cache_alignment() /* for alignment */)
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/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
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struct mpsc_rx_desc {
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u16 bufsize;
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u16 bytecnt;
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u32 cmdstat;
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u32 link;
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u32 buf_ptr;
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} __attribute((packed));
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struct mpsc_tx_desc {
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u16 bytecnt;
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u16 shadow;
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u32 cmdstat;
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u32 link;
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u32 buf_ptr;
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} __attribute((packed));
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/*
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* Some regs that have the erratum that you can't read them are are shared
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* between the two MPSC controllers. This struct contains those shared regs.
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*/
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struct mpsc_shared_regs {
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phys_addr_t mpsc_routing_base_p;
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phys_addr_t sdma_intr_base_p;
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void __iomem *mpsc_routing_base;
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void __iomem *sdma_intr_base;
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u32 MPSC_MRR_m;
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u32 MPSC_RCRR_m;
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u32 MPSC_TCRR_m;
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u32 SDMA_INTR_CAUSE_m;
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u32 SDMA_INTR_MASK_m;
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};
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/* The main driver data structure */
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struct mpsc_port_info {
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struct uart_port port; /* Overlay uart_port structure */
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/* Internal driver state for this ctlr */
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u8 ready;
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u8 rcv_data;
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tcflag_t c_iflag; /* save termios->c_iflag */
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tcflag_t c_cflag; /* save termios->c_cflag */
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/* Info passed in from platform */
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u8 mirror_regs; /* Need to mirror regs? */
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u8 cache_mgmt; /* Need manual cache mgmt? */
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u8 brg_can_tune; /* BRG has baud tuning? */
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u32 brg_clk_src;
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u16 mpsc_max_idle;
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int default_baud;
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int default_bits;
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int default_parity;
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int default_flow;
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/* Physical addresses of various blocks of registers (from platform) */
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phys_addr_t mpsc_base_p;
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phys_addr_t sdma_base_p;
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phys_addr_t brg_base_p;
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/* Virtual addresses of various blocks of registers (from platform) */
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void __iomem *mpsc_base;
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void __iomem *sdma_base;
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void __iomem *brg_base;
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/* Descriptor ring and buffer allocations */
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void *dma_region;
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dma_addr_t dma_region_p;
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dma_addr_t rxr; /* Rx descriptor ring */
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dma_addr_t rxr_p; /* Phys addr of rxr */
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u8 *rxb; /* Rx Ring I/O buf */
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u8 *rxb_p; /* Phys addr of rxb */
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u32 rxr_posn; /* First desc w/ Rx data */
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dma_addr_t txr; /* Tx descriptor ring */
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dma_addr_t txr_p; /* Phys addr of txr */
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u8 *txb; /* Tx Ring I/O buf */
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u8 *txb_p; /* Phys addr of txb */
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int txr_head; /* Where new data goes */
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int txr_tail; /* Where sent data comes off */
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/* Mirrored values of regs we can't read (if 'mirror_regs' set) */
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u32 MPSC_MPCR_m;
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u32 MPSC_CHR_1_m;
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u32 MPSC_CHR_2_m;
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u32 MPSC_CHR_10_m;
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u32 BRG_BCR_m;
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struct mpsc_shared_regs *shared_regs;
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};
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/* Hooks to platform-specific code */
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int mpsc_platform_register_driver(void);
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void mpsc_platform_unregister_driver(void);
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/* Hooks back in to mpsc common to be called by platform-specific code */
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struct mpsc_port_info *mpsc_device_probe(int index);
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struct mpsc_port_info *mpsc_device_remove(int index);
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/*
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*****************************************************************************
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*
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* Multi-Protocol Serial Controller Interface Registers
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*
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*****************************************************************************
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*/
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/* Main Configuratino Register Offsets */
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#define MPSC_MMCRL 0x0000
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#define MPSC_MMCRH 0x0004
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#define MPSC_MPCR 0x0008
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#define MPSC_CHR_1 0x000c
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#define MPSC_CHR_2 0x0010
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#define MPSC_CHR_3 0x0014
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#define MPSC_CHR_4 0x0018
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#define MPSC_CHR_5 0x001c
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#define MPSC_CHR_6 0x0020
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#define MPSC_CHR_7 0x0024
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#define MPSC_CHR_8 0x0028
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#define MPSC_CHR_9 0x002c
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#define MPSC_CHR_10 0x0030
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#define MPSC_CHR_11 0x0034
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#define MPSC_MPCR_FRZ (1 << 9)
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#define MPSC_MPCR_CL_5 0
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#define MPSC_MPCR_CL_6 1
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#define MPSC_MPCR_CL_7 2
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#define MPSC_MPCR_CL_8 3
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#define MPSC_MPCR_SBL_1 0
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#define MPSC_MPCR_SBL_2 1
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#define MPSC_CHR_2_TEV (1<<1)
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#define MPSC_CHR_2_TA (1<<7)
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#define MPSC_CHR_2_TTCS (1<<9)
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#define MPSC_CHR_2_REV (1<<17)
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#define MPSC_CHR_2_RA (1<<23)
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#define MPSC_CHR_2_CRD (1<<25)
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#define MPSC_CHR_2_EH (1<<31)
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#define MPSC_CHR_2_PAR_ODD 0
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#define MPSC_CHR_2_PAR_SPACE 1
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#define MPSC_CHR_2_PAR_EVEN 2
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#define MPSC_CHR_2_PAR_MARK 3
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/* MPSC Signal Routing */
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#define MPSC_MRR 0x0000
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#define MPSC_RCRR 0x0004
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#define MPSC_TCRR 0x0008
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/*
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*****************************************************************************
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*
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* Serial DMA Controller Interface Registers
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*
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*****************************************************************************
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*/
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#define SDMA_SDC 0x0000
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#define SDMA_SDCM 0x0008
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#define SDMA_RX_DESC 0x0800
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#define SDMA_RX_BUF_PTR 0x0808
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#define SDMA_SCRDP 0x0810
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#define SDMA_TX_DESC 0x0c00
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#define SDMA_SCTDP 0x0c10
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#define SDMA_SFTDP 0x0c14
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#define SDMA_DESC_CMDSTAT_PE (1<<0)
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#define SDMA_DESC_CMDSTAT_CDL (1<<1)
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#define SDMA_DESC_CMDSTAT_FR (1<<3)
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#define SDMA_DESC_CMDSTAT_OR (1<<6)
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#define SDMA_DESC_CMDSTAT_BR (1<<9)
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#define SDMA_DESC_CMDSTAT_MI (1<<10)
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#define SDMA_DESC_CMDSTAT_A (1<<11)
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#define SDMA_DESC_CMDSTAT_AM (1<<12)
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#define SDMA_DESC_CMDSTAT_CT (1<<13)
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#define SDMA_DESC_CMDSTAT_C (1<<14)
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#define SDMA_DESC_CMDSTAT_ES (1<<15)
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#define SDMA_DESC_CMDSTAT_L (1<<16)
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#define SDMA_DESC_CMDSTAT_F (1<<17)
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#define SDMA_DESC_CMDSTAT_P (1<<18)
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#define SDMA_DESC_CMDSTAT_EI (1<<23)
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#define SDMA_DESC_CMDSTAT_O (1<<31)
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#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
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SDMA_DESC_CMDSTAT_EI)
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#define SDMA_SDC_RFT (1<<0)
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#define SDMA_SDC_SFM (1<<1)
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#define SDMA_SDC_BLMR (1<<6)
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#define SDMA_SDC_BLMT (1<<7)
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#define SDMA_SDC_POVR (1<<8)
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#define SDMA_SDC_RIFB (1<<9)
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#define SDMA_SDCM_ERD (1<<7)
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#define SDMA_SDCM_AR (1<<15)
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#define SDMA_SDCM_STD (1<<16)
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#define SDMA_SDCM_TXD (1<<23)
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#define SDMA_SDCM_AT (1<<31)
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#define SDMA_0_CAUSE_RXBUF (1<<0)
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#define SDMA_0_CAUSE_RXERR (1<<1)
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#define SDMA_0_CAUSE_TXBUF (1<<2)
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#define SDMA_0_CAUSE_TXEND (1<<3)
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#define SDMA_1_CAUSE_RXBUF (1<<8)
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#define SDMA_1_CAUSE_RXERR (1<<9)
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#define SDMA_1_CAUSE_TXBUF (1<<10)
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#define SDMA_1_CAUSE_TXEND (1<<11)
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#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
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SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
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#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
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SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
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/* SDMA Interrupt registers */
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#define SDMA_INTR_CAUSE 0x0000
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#define SDMA_INTR_MASK 0x0080
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/*
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*****************************************************************************
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*
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* Baud Rate Generator Interface Registers
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*
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*****************************************************************************
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*/
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#define BRG_BCR 0x0000
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#define BRG_BTR 0x0004
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#endif /* __MPSC_H__ */
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