cf8de5a7f8
This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
37 lines
1.1 KiB
C
37 lines
1.1 KiB
C
/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __BERLIN2_PLL_H
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#define __BERLIN2_PLL_H
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struct clk;
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struct berlin2_pll_map {
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const u8 vcodiv[16];
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u8 mult;
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u8 fbdiv_shift;
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u8 rfdiv_shift;
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u8 divsel_shift;
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};
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struct clk * __init
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berlin2_pll_register(const struct berlin2_pll_map *map,
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void __iomem *base, const char *name,
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const char *parent_name, unsigned long flags);
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#endif /* __BERLIN2_PLL_H */
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