69cfb41941
A few small functions were called only by other functions in the same file, so merge them together. One function, for example, was calculating the device address even though the caller was doing the same thing. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
428 lines
10 KiB
C
428 lines
10 KiB
C
/*
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* Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
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* Provides Bus interface for MIIM regs
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*
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* Author: Andy Fleming <afleming@freescale.com>
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* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
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*
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* Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
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*
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* Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mii.h>
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#include <linux/of_address.h>
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#include <linux/of_mdio.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */
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#include "gianfar.h"
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#define MIIMIND_BUSY 0x00000001
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#define MIIMIND_NOTVALID 0x00000004
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#define MIIMCFG_INIT_VALUE 0x00000007
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#define MIIMCFG_RESET 0x80000000
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#define MII_READ_COMMAND 0x00000001
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struct fsl_pq_mdio {
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u8 res1[16];
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u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
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u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
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u8 res2[4];
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u32 emapm; /* MDIO Event mapping register (for etsec2)*/
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u8 res3[1280];
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u32 miimcfg; /* MII management configuration reg */
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u32 miimcom; /* MII management command reg */
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u32 miimadd; /* MII management address reg */
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u32 miimcon; /* MII management control reg */
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u32 miimstat; /* MII management status reg */
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u32 miimind; /* MII management indication reg */
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u8 res4[28];
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u32 utbipar; /* TBI phy address reg (only on UCC) */
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u8 res5[2728];
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} __packed;
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/* Number of microseconds to wait for an MII register to respond */
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#define MII_TIMEOUT 1000
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struct fsl_pq_mdio_priv {
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void __iomem *map;
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struct fsl_pq_mdio __iomem *regs;
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};
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/*
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* Write value to the PHY at mii_id at register regnum, on the bus attached
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* to the local interface, which may be different from the generic mdio bus
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* (tied to a single interface), waiting until the write is done before
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* returning. This is helpful in programming interfaces like the TBI which
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* control interfaces like onchip SERDES and are always tied to the local
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* mdio pins, which may not be the same as system mdio bus, used for
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* controlling the external PHYs, for example.
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*/
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static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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u16 value)
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{
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struct fsl_pq_mdio_priv *priv = bus->priv;
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struct fsl_pq_mdio __iomem *regs = priv->regs;
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u32 status;
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/* Set the PHY address and the register address we want to write */
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out_be32(®s->miimadd, (mii_id << 8) | regnum);
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/* Write out the value we want */
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out_be32(®s->miimcon, value);
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/* Wait for the transaction to finish */
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status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY),
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MII_TIMEOUT, 0);
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return status ? 0 : -ETIMEDOUT;
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}
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/*
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* Read the bus for PHY at addr mii_id, register regnum, and return the value.
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* Clears miimcom first.
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*
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* All PHY operation done on the bus attached to the local interface, which
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* may be different from the generic mdio bus. This is helpful in programming
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* interfaces like the TBI which, in turn, control interfaces like on-chip
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* SERDES and are always tied to the local mdio pins, which may not be the
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* same as system mdio bus, used for controlling the external PHYs, for eg.
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*/
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static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct fsl_pq_mdio_priv *priv = bus->priv;
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struct fsl_pq_mdio __iomem *regs = priv->regs;
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u32 status;
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u16 value;
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/* Set the PHY address and the register address we want to read */
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out_be32(®s->miimadd, (mii_id << 8) | regnum);
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/* Clear miimcom, and then initiate a read */
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out_be32(®s->miimcom, 0);
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out_be32(®s->miimcom, MII_READ_COMMAND);
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/* Wait for the transaction to finish, normally less than 100us */
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status = spin_event_timeout(!(in_be32(®s->miimind) &
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(MIIMIND_NOTVALID | MIIMIND_BUSY)),
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MII_TIMEOUT, 0);
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if (!status)
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return -ETIMEDOUT;
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/* Grab the value of the register from miimstat */
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value = in_be32(®s->miimstat);
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return value;
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}
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/* Reset the MIIM registers, and wait for the bus to free */
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static int fsl_pq_mdio_reset(struct mii_bus *bus)
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{
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struct fsl_pq_mdio_priv *priv = bus->priv;
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struct fsl_pq_mdio __iomem *regs = priv->regs;
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u32 status;
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mutex_lock(&bus->mdio_lock);
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/* Reset the management interface */
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out_be32(®s->miimcfg, MIIMCFG_RESET);
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/* Setup the MII Mgmt clock speed */
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out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
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/* Wait until the bus is free */
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status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY),
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MII_TIMEOUT, 0);
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mutex_unlock(&bus->mdio_lock);
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if (!status) {
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printk(KERN_ERR "%s: The MII Bus is stuck!\n",
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bus->name);
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return -EBUSY;
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}
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return 0;
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}
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static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
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{
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#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
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struct gfar __iomem *enet_regs;
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/*
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* This is mildly evil, but so is our hardware for doing this.
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* Also, we have to cast back to struct gfar because of
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* definition weirdness done in gianfar.h.
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*/
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if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
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of_device_is_compatible(np, "fsl,gianfar-tbi") ||
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of_device_is_compatible(np, "gianfar")) {
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enet_regs = (struct gfar __iomem *)regs;
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return &enet_regs->tbipa;
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} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
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of_device_is_compatible(np, "fsl,etsec2-tbi")) {
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return of_iomap(np, 1);
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}
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#endif
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return NULL;
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}
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static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
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{
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#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
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struct device_node *np = NULL;
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int err = 0;
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for_each_compatible_node(np, NULL, "ucc_geth") {
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struct resource tempres;
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err = of_address_to_resource(np, 0, &tempres);
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if (err)
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continue;
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/* if our mdio regs fall within this UCC regs range */
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if ((start >= tempres.start) && (end <= tempres.end)) {
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/* Find the id of the UCC */
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const u32 *id;
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id = of_get_property(np, "cell-index", NULL);
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if (!id) {
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id = of_get_property(np, "device-id", NULL);
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if (!id)
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continue;
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}
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*ucc_id = *id;
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return 0;
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}
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}
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if (err)
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return err;
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else
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return -EINVAL;
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#else
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return -ENODEV;
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#endif
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}
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static int fsl_pq_mdio_probe(struct platform_device *ofdev)
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{
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struct device_node *np = ofdev->dev.of_node;
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struct device_node *tbi;
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struct fsl_pq_mdio_priv *priv;
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struct fsl_pq_mdio __iomem *regs = NULL;
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void __iomem *map;
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u32 __iomem *tbipa;
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struct mii_bus *new_bus;
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int tbiaddr = -1;
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const u32 *addrp;
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u64 addr = 0, size = 0;
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int err;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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new_bus = mdiobus_alloc();
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if (!new_bus) {
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err = -ENOMEM;
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goto err_free_priv;
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}
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new_bus->name = "Freescale PowerQUICC MII Bus",
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new_bus->read = &fsl_pq_mdio_read,
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new_bus->write = &fsl_pq_mdio_write,
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new_bus->reset = &fsl_pq_mdio_reset,
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new_bus->priv = priv;
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addrp = of_get_address(np, 0, &size, NULL);
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if (!addrp) {
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err = -EINVAL;
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goto err_free_bus;
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}
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/* Set the PHY base address */
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addr = of_translate_address(np, addrp);
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if (addr == OF_BAD_ADDR) {
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err = -EINVAL;
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goto err_free_bus;
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}
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snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
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(unsigned long long)addr);
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map = ioremap(addr, size);
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if (!map) {
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err = -ENOMEM;
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goto err_free_bus;
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}
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priv->map = map;
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if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
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of_device_is_compatible(np, "fsl,gianfar-tbi") ||
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of_device_is_compatible(np, "fsl,ucc-mdio") ||
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of_device_is_compatible(np, "ucc_geth_phy"))
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map -= offsetof(struct fsl_pq_mdio, miimcfg);
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regs = map;
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priv->regs = regs;
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new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
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if (NULL == new_bus->irq) {
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err = -ENOMEM;
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goto err_unmap_regs;
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}
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new_bus->parent = &ofdev->dev;
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dev_set_drvdata(&ofdev->dev, new_bus);
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if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
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of_device_is_compatible(np, "fsl,gianfar-tbi") ||
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of_device_is_compatible(np, "fsl,etsec2-mdio") ||
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of_device_is_compatible(np, "fsl,etsec2-tbi") ||
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of_device_is_compatible(np, "gianfar")) {
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tbipa = get_gfar_tbipa(regs, np);
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if (!tbipa) {
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err = -EINVAL;
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goto err_free_irqs;
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}
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} else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
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of_device_is_compatible(np, "ucc_geth_phy")) {
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u32 id;
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static u32 mii_mng_master;
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tbipa = ®s->utbipar;
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if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
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goto err_free_irqs;
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if (!mii_mng_master) {
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mii_mng_master = id;
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ucc_set_qe_mux_mii_mng(id - 1);
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}
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} else {
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err = -ENODEV;
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goto err_free_irqs;
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}
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for_each_child_of_node(np, tbi) {
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if (!strncmp(tbi->type, "tbi-phy", 8))
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break;
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}
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if (tbi) {
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const u32 *prop = of_get_property(tbi, "reg", NULL);
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if (prop)
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tbiaddr = *prop;
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if (tbiaddr == -1) {
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err = -EBUSY;
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goto err_free_irqs;
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} else {
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out_be32(tbipa, tbiaddr);
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}
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}
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err = of_mdiobus_register(new_bus, np);
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if (err) {
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printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
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new_bus->name);
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goto err_free_irqs;
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}
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return 0;
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err_free_irqs:
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kfree(new_bus->irq);
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err_unmap_regs:
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iounmap(priv->map);
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err_free_bus:
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kfree(new_bus);
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err_free_priv:
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kfree(priv);
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return err;
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}
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static int fsl_pq_mdio_remove(struct platform_device *ofdev)
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{
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struct device *device = &ofdev->dev;
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struct mii_bus *bus = dev_get_drvdata(device);
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struct fsl_pq_mdio_priv *priv = bus->priv;
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mdiobus_unregister(bus);
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dev_set_drvdata(device, NULL);
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iounmap(priv->map);
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bus->priv = NULL;
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mdiobus_free(bus);
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kfree(priv);
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return 0;
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}
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static struct of_device_id fsl_pq_mdio_match[] = {
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{
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.type = "mdio",
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.compatible = "ucc_geth_phy",
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},
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{
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.type = "mdio",
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.compatible = "gianfar",
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},
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{
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.compatible = "fsl,ucc-mdio",
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},
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{
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.compatible = "fsl,gianfar-tbi",
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},
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{
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.compatible = "fsl,gianfar-mdio",
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},
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{
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.compatible = "fsl,etsec2-tbi",
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},
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{
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.compatible = "fsl,etsec2-mdio",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
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static struct platform_driver fsl_pq_mdio_driver = {
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.driver = {
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.name = "fsl-pq_mdio",
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.owner = THIS_MODULE,
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.of_match_table = fsl_pq_mdio_match,
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},
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.probe = fsl_pq_mdio_probe,
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.remove = fsl_pq_mdio_remove,
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};
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module_platform_driver(fsl_pq_mdio_driver);
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MODULE_LICENSE("GPL");
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