69d4255b13
Add more barriers in the SRAM CORE DPLL M2 divider change code. - Add a DSB SY after the function's entry point to flush all cached and buffered writes and wait for the interconnect to claim that they have completed[1]. The idea here is to force all delayed write traffic going to the SDRAM to at least post to the L3 interconnect before continuing. If these writes are allowed to occur after the SDRC is idled, the writes will not be acknowledged and the ARM will stall. Note that in this case, it does not matter if the writes actually complete to the SDRAM - it is only necessary for the writes to leave the ARM itself. If the writes are posted by the interconnect when the SDRC goes into idle, the writes will be delayed until the SDRC returns from idle[2]. If the SDRC is in the middle of a write when it is requested to enter idle, the SDRC will not acknowledge the idle request until the writes complete to the SDRAM.[3] The old-style DMB in sdram_in_selfrefresh is now superfluous, so, remove it. - Add an ISB before the function's exit point to prevent the ARM from speculatively executing into SDRAM before the SDRAM is enabled[4]. ... 1. ARMv7 ARM (DDI 0406A) A3-47, A3-48. 2. Private communication with Richard Woodruff <r-woodruff2@ti.com>. 3. Private communication with Richard Woodruff <r-woodruff2@ti.com>. 4. ARMv7 ARM (DDI 0406A) A3-48. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
179 lines
4.3 KiB
ArmAsm
179 lines
4.3 KiB
ArmAsm
/*
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* linux/arch/arm/mach-omap3/sram.S
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*
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* Omap3 specific functions that need to be run in internal SRAM
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*
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* (C) Copyright 2007
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* Texas Instruments Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include "sdrc.h"
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#include "cm.h"
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.text
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/*
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* Change frequency of core dpll
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* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2
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blne configure_sdrc
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cmp r3, #0x2
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blne lock_dll
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cmp r3, #0x1
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blne unlock_dll
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bl sdram_in_selfrefresh @ put the SDRAM in self refresh
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bl configure_core_dpll
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bl enable_sdrc
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cmp r3, #0x1
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blne wait_dll_unlock
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cmp r3, #0x2
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blne wait_dll_lock
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cmp r3, #0x1
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blne configure_sdrc
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isb @ prevent speculative exec past here
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mov r0, #0 @ return value
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ldmfd sp!, {r1-r12, pc} @ restore regs and return
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unlock_dll:
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ldr r4, omap3_sdrc_dlla_ctrl
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ldr r5, [r4]
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orr r5, r5, #0x4
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str r5, [r4]
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bx lr
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lock_dll:
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ldr r4, omap3_sdrc_dlla_ctrl
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ldr r5, [r4]
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bic r5, r5, #0x4
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str r5, [r4]
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bx lr
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sdram_in_selfrefresh:
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ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r5, [r4] @ read the contents of SDRC_POWER
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orr r5, r5, #0x40 @ enable self refresh on idle req
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str r5, [r4] @ write back to SDRC_POWER register
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ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r5, [r4]
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bic r5, r5, #0x2 @ disable iclk bit for SRDC
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str r5, [r4]
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wait_sdrc_idle:
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ldr r4, omap3_cm_idlest1_core
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ldr r5, [r4]
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and r5, r5, #0x2 @ check for SDRC idle
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cmp r5, #2
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bne wait_sdrc_idle
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bx lr
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configure_core_dpll:
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ldr r4, omap3_cm_clksel1_pll
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ldr r5, [r4]
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ldr r6, core_m2_mask_val @ modify m2 for core dpll
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and r5, r5, r6
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orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
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str r5, [r4]
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mov r5, #0x800 @ wait for the clock to stabilise
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cmp r3, #2
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bne wait_clk_stable
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bx lr
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wait_clk_stable:
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subs r5, r5, #1
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bne wait_clk_stable
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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bx lr
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enable_sdrc:
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ldr r4, omap3_cm_iclken1_core
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ldr r5, [r4]
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orr r5, r5, #0x2 @ enable iclk bit for SDRC
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str r5, [r4]
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wait_sdrc_idle1:
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ldr r4, omap3_cm_idlest1_core
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ldr r5, [r4]
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and r5, r5, #0x2
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cmp r5, #0
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bne wait_sdrc_idle1
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ldr r4, omap3_sdrc_power
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ldr r5, [r4]
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bic r5, r5, #0x40
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str r5, [r4]
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bx lr
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wait_dll_lock:
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ldr r4, omap3_sdrc_dlla_status
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ldr r5, [r4]
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and r5, r5, #0x4
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cmp r5, #0x4
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bne wait_dll_lock
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bx lr
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wait_dll_unlock:
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ldr r4, omap3_sdrc_dlla_status
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ldr r5, [r4]
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and r5, r5, #0x4
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cmp r5, #0x0
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bne wait_dll_unlock
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bx lr
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configure_sdrc:
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ldr r4, omap3_sdrc_rfr_ctrl
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str r0, [r4]
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ldr r4, omap3_sdrc_actim_ctrla
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str r1, [r4]
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ldr r4, omap3_sdrc_actim_ctrlb
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str r2, [r4]
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bx lr
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omap3_sdrc_power:
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.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
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omap3_cm_clksel1_pll:
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.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
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omap3_cm_idlest1_core:
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.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
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omap3_cm_iclken1_core:
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.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
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omap3_sdrc_rfr_ctrl:
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.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
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omap3_sdrc_actim_ctrla:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
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omap3_sdrc_actim_ctrlb:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
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omap3_sdrc_dlla_status:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
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omap3_sdrc_dlla_ctrl:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
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core_m2_mask_val:
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.word 0x07FFFFFF
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ENTRY(omap3_sram_configure_core_dpll_sz)
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.word . - omap3_sram_configure_core_dpll
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