linux-hardened/drivers/gpu
Ville Syrjälä 6fe6a7ffd3 drm/i915: Zero out HOWM registers before writing new WM/HOWM register values
On VLV/CHV some of the watermark values are split across two registers:
low order bits in one, and high order bits in another. So we may not be
able to update a single watermark value atomically, and thus we must be
careful that we don't temporarily introduce out of bounds values during
the reprogramming. To prevent this we can simply zero out all the high
order bits initially, then we update the low order bits, and finally
we update the high order bits with the final value.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-13-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:27 +02:00
..
drm drm/i915: Zero out HOWM registers before writing new WM/HOWM register values 2016-12-05 16:23:27 +02:00
host1x drm/tegra: dsi: Enhance runtime power management 2016-08-24 15:58:57 +02:00
ipu-v3 imx-drm plane update cleanup, YUV formats 2016-11-11 09:31:27 +10:00
vga vgaarb: use valid dev pointer in vgaarb_info() 2016-11-22 16:40:35 +01:00
Makefile