1af897dff6
There is no SPEAr600 device named "wdt". Instead, the description of the WDT (watchdog) was recently added to the Device Tree, and the device name is "fc880000.wdt", so we should associate the WDT fixed rate clock to this device name. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
340 lines
12 KiB
C
340 lines
12 KiB
C
/*
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* SPEAr6xx machines clock framework source file
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <vireshk@kernel.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/spinlock_types.h>
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#include "clk.h"
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static DEFINE_SPINLOCK(_lock);
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#define PLL1_CTR (misc_base + 0x008)
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#define PLL1_FRQ (misc_base + 0x00C)
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#define PLL2_CTR (misc_base + 0x014)
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#define PLL2_FRQ (misc_base + 0x018)
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#define PLL_CLK_CFG (misc_base + 0x020)
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/* PLL_CLK_CFG register masks */
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#define MCTR_CLK_SHIFT 28
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#define MCTR_CLK_MASK 3
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#define CORE_CLK_CFG (misc_base + 0x024)
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/* CORE CLK CFG register masks */
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#define HCLK_RATIO_SHIFT 10
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#define HCLK_RATIO_MASK 2
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#define PCLK_RATIO_SHIFT 8
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#define PCLK_RATIO_MASK 2
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#define PERIP_CLK_CFG (misc_base + 0x028)
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/* PERIP_CLK_CFG register masks */
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#define CLCD_CLK_SHIFT 2
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#define CLCD_CLK_MASK 2
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#define UART_CLK_SHIFT 4
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#define UART_CLK_MASK 1
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#define FIRDA_CLK_SHIFT 5
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#define FIRDA_CLK_MASK 2
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#define GPT0_CLK_SHIFT 8
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#define GPT1_CLK_SHIFT 10
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#define GPT2_CLK_SHIFT 11
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#define GPT3_CLK_SHIFT 12
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#define GPT_CLK_MASK 1
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#define PERIP1_CLK_ENB (misc_base + 0x02C)
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/* PERIP1_CLK_ENB register masks */
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#define UART0_CLK_ENB 3
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#define UART1_CLK_ENB 4
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#define SSP0_CLK_ENB 5
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#define SSP1_CLK_ENB 6
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#define I2C_CLK_ENB 7
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#define JPEG_CLK_ENB 8
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#define FSMC_CLK_ENB 9
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#define FIRDA_CLK_ENB 10
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#define GPT2_CLK_ENB 11
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#define GPT3_CLK_ENB 12
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#define GPIO2_CLK_ENB 13
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#define SSP2_CLK_ENB 14
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#define ADC_CLK_ENB 15
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#define GPT1_CLK_ENB 11
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#define RTC_CLK_ENB 17
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#define GPIO1_CLK_ENB 18
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#define DMA_CLK_ENB 19
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#define SMI_CLK_ENB 21
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#define CLCD_CLK_ENB 22
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#define GMAC_CLK_ENB 23
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#define USBD_CLK_ENB 24
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#define USBH0_CLK_ENB 25
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#define USBH1_CLK_ENB 26
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#define PRSC0_CLK_CFG (misc_base + 0x044)
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#define PRSC1_CLK_CFG (misc_base + 0x048)
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#define PRSC2_CLK_CFG (misc_base + 0x04C)
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#define CLCD_CLK_SYNT (misc_base + 0x05C)
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#define FIRDA_CLK_SYNT (misc_base + 0x060)
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#define UART_CLK_SYNT (misc_base + 0x064)
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/* vco rate configuration table, in ascending order of rates */
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static struct pll_rate_tbl pll_rtbl[] = {
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{.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
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{.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
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{.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
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};
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/* aux rate configuration table, in ascending order of rates */
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static struct aux_rate_tbl aux_rtbl[] = {
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/* For PLL1 = 332 MHz */
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{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
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{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
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{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
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{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
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};
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static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
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static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
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static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
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static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
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static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
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static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
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static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
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"pll2_clk", };
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/* gpt rate configuration table, in ascending order of rates */
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static struct gpt_rate_tbl gpt_rtbl[] = {
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/* For pll1 = 332 MHz */
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{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
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{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
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{.mscale = 1, .nscale = 0}, /* 83 MHz */
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};
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void __init spear6xx_clk_init(void __iomem *misc_base)
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{
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struct clk *clk, *clk1;
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clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
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clk_register_clkdev(clk, "osc_32k_clk", NULL);
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clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
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clk_register_clkdev(clk, "osc_30m_clk", NULL);
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/* clock derived from 32 KHz osc clk */
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clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
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PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "rtc-spear");
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/* clock derived from 30 MHz osc clk */
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clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
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48000000);
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clk_register_clkdev(clk, "pll3_clk", NULL);
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clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
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0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
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&_lock, &clk1, NULL);
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clk_register_clkdev(clk, "vco1_clk", NULL);
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clk_register_clkdev(clk1, "pll1_clk", NULL);
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clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
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0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
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&_lock, &clk1, NULL);
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clk_register_clkdev(clk, "vco2_clk", NULL);
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clk_register_clkdev(clk1, "pll2_clk", NULL);
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clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
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1);
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clk_register_clkdev(clk, NULL, "fc880000.wdt");
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/* clock derived from pll1 clk */
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clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
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CLK_SET_RATE_PARENT, 1, 1);
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clk_register_clkdev(clk, "cpu_clk", NULL);
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clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
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CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
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HCLK_RATIO_MASK, 0, &_lock);
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clk_register_clkdev(clk, "ahb_clk", NULL);
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clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
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UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "uart_syn_clk", NULL);
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clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
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ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
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&_lock);
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clk_register_clkdev(clk, "uart_mclk", NULL);
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clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
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UART0_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d0000000.serial");
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clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
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UART1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d0080000.serial");
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clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
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0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "firda_syn_clk", NULL);
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clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
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ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
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&_lock);
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clk_register_clkdev(clk, "firda_mclk", NULL);
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clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
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PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "firda");
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clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
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0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "clcd_syn_clk", NULL);
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clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
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ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
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&_lock);
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clk_register_clkdev(clk, "clcd_mclk", NULL);
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clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
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PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "clcd");
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/* gpt clocks */
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clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
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clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
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ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt0");
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clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
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ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt1_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
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PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt1");
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clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
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clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
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ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt2_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
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PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt2");
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clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
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clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
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ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt3_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
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PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt3");
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/* clock derived from pll3 clk */
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clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
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PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "e1800000.ehci");
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clk_register_clkdev(clk, NULL, "e1900000.ohci");
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clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
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PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "e2000000.ehci");
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clk_register_clkdev(clk, NULL, "e2100000.ohci");
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clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
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USBD_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "designware_udc");
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/* clock derived from ahb clk */
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clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
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1);
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clk_register_clkdev(clk, "ahbmult2_clk", NULL);
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clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
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ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
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PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "ddr_clk", NULL);
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clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
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CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
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PCLK_RATIO_MASK, 0, &_lock);
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clk_register_clkdev(clk, "apb_clk", NULL);
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clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
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DMA_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "fc400000.dma");
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clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
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FSMC_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d1800000.flash");
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clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
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GMAC_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "e0800000.ethernet");
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clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
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I2C_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d0200000.i2c");
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clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
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JPEG_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "jpeg");
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clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
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SMI_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "fc000000.flash");
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/* clock derived from apb clk */
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clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
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ADC_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d820b000.adc");
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clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
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clk_register_clkdev(clk, NULL, "f0100000.gpio");
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clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
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GPIO1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "fc980000.gpio");
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clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
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GPIO2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d8100000.gpio");
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clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
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SSP0_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "ssp-pl022.0");
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clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
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SSP1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "ssp-pl022.1");
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clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
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SSP2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "ssp-pl022.2");
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}
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