b8eb71dcdd
Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
57 lines
1.4 KiB
C
57 lines
1.4 KiB
C
/*
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* Copyright 2016 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CCU_SUN9I_A80_H_
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#define _CCU_SUN9I_A80_H_
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#include <dt-bindings/clock/sun9i-a80-ccu.h>
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#include <dt-bindings/reset/sun9i-a80-ccu.h>
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#define CLK_PLL_C0CPUX 0
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#define CLK_PLL_C1CPUX 1
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/* pll-audio and pll-periph0 are exported to the PRCM block */
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#define CLK_PLL_VE 4
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#define CLK_PLL_DDR 5
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#define CLK_PLL_VIDEO0 6
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#define CLK_PLL_VIDEO1 7
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#define CLK_PLL_GPU 8
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#define CLK_PLL_DE 9
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#define CLK_PLL_ISP 10
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#define CLK_PLL_PERIPH1 11
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/* The CPUX clocks are exported */
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#define CLK_ATB0 14
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#define CLK_AXI0 15
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#define CLK_ATB1 16
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#define CLK_AXI1 17
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#define CLK_GTBUS 18
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#define CLK_AHB0 19
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#define CLK_AHB1 20
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#define CLK_AHB2 21
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#define CLK_APB0 22
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#define CLK_APB1 23
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#define CLK_CCI400 24
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#define CLK_ATS 25
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#define CLK_TRACE 26
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/* module clocks and bus gates exported */
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#define CLK_NUMBER (CLK_BUS_UART5 + 1)
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#endif /* _CCU_SUN9I_A80_H_ */
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