ac8616e4c8
The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.
This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.
Cc: stable@vger.kernel.org
Fixes: 2ab836db50
("clk: sunxi-ng: Add M-P factor clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
173 lines
4.1 KiB
C
173 lines
4.1 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
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unsigned int max_m, unsigned int max_p,
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unsigned int *m, unsigned int *p)
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{
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unsigned long best_rate = 0;
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unsigned int best_m = 0, best_p = 0;
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unsigned int _m, _p;
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for (_p = 1; _p <= max_p; _p <<= 1) {
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for (_m = 1; _m <= max_m; _m++) {
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unsigned long tmp_rate = parent / _p / _m;
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if (tmp_rate > rate)
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continue;
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if ((rate - tmp_rate) < (rate - best_rate)) {
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best_rate = tmp_rate;
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best_m = _m;
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best_p = _p;
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}
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}
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}
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*m = best_m;
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*p = best_p;
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}
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static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
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unsigned long parent_rate,
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unsigned long rate,
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void *data)
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{
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struct ccu_mp *cmp = data;
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unsigned int max_m, max_p;
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unsigned int m, p;
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max_m = cmp->m.max ?: 1 << cmp->m.width;
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max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
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ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
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return parent_rate / p / m;
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}
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static void ccu_mp_disable(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_gate_helper_disable(&cmp->common, cmp->enable);
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}
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static int ccu_mp_enable(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_gate_helper_enable(&cmp->common, cmp->enable);
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}
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static int ccu_mp_is_enabled(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);
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}
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static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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unsigned int m, p;
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u32 reg;
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/* Adjust parent_rate according to pre-dividers */
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ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
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-1, &parent_rate);
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reg = readl(cmp->common.base + cmp->common.reg);
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m = reg >> cmp->m.shift;
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m &= (1 << cmp->m.width) - 1;
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m += cmp->m.offset;
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if (!m)
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m++;
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p = reg >> cmp->p.shift;
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p &= (1 << cmp->p.width) - 1;
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return (parent_rate >> p) / m;
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}
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static int ccu_mp_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,
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req, ccu_mp_round_rate, cmp);
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}
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static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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unsigned long flags;
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unsigned int max_m, max_p;
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unsigned int m, p;
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u32 reg;
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/* Adjust parent_rate according to pre-dividers */
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ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
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-1, &parent_rate);
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max_m = cmp->m.max ?: 1 << cmp->m.width;
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max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
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ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
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spin_lock_irqsave(cmp->common.lock, flags);
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reg = readl(cmp->common.base + cmp->common.reg);
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reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
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reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
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reg |= (m - cmp->m.offset) << cmp->m.shift;
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reg |= ilog2(p) << cmp->p.shift;
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writel(reg, cmp->common.base + cmp->common.reg);
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spin_unlock_irqrestore(cmp->common.lock, flags);
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return 0;
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}
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static u8 ccu_mp_get_parent(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);
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}
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static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);
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}
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const struct clk_ops ccu_mp_ops = {
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.disable = ccu_mp_disable,
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.enable = ccu_mp_enable,
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.is_enabled = ccu_mp_is_enabled,
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.get_parent = ccu_mp_get_parent,
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.set_parent = ccu_mp_set_parent,
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.determine_rate = ccu_mp_determine_rate,
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.recalc_rate = ccu_mp_recalc_rate,
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.set_rate = ccu_mp_set_rate,
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};
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