808e738142
To support guest PMUv3, use one bit of the VCPU INIT feature array. Initialize the PMU when initialzing the vcpu with that bit and PMU overflow interrupt set. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
87 lines
3.1 KiB
C
87 lines
3.1 KiB
C
/*
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Shannon Zhao <shannon.zhao@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARM_KVM_PMU_H
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#define __ASM_ARM_KVM_PMU_H
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#ifdef CONFIG_KVM_ARM_PMU
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#include <linux/perf_event.h>
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#include <asm/perf_event.h>
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#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
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struct kvm_pmc {
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u8 idx; /* index into the pmu->pmc array */
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struct perf_event *perf_event;
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u64 bitmask;
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};
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struct kvm_pmu {
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int irq_num;
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struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
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bool ready;
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bool irq_level;
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};
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#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
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void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
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u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
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void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
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void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
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u64 select_idx);
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bool kvm_arm_support_pmu_v3(void);
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#else
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struct kvm_pmu {
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};
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#define kvm_arm_pmu_v3_ready(v) (false)
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static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx)
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{
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return 0;
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}
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static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx, u64 val) {}
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static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
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u64 data, u64 select_idx) {}
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static inline bool kvm_arm_support_pmu_v3(void) { return false; }
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#endif
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#endif
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