ebb945a94b
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
96 lines
3 KiB
C
96 lines
3 KiB
C
/*
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* Copyright (C) 2008 Maarten Maathuis.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NV50_DISPLAY_H__
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#define __NV50_DISPLAY_H__
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include "nouveau_reg.h"
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#include "nouveau_crtc.h"
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#include "nv50_evo.h"
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struct nv50_display_crtc {
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struct nouveau_channel *sync;
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struct {
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struct nouveau_bo *bo;
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u32 offset;
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u16 value;
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} sem;
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};
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struct nv50_display {
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struct nouveau_channel *master;
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struct nouveau_gpuobj *ramin;
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u32 dmao;
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u32 hash;
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struct nv50_display_crtc crtc[2];
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struct tasklet_struct tasklet;
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struct {
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struct dcb_output *dcb;
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u16 script;
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u32 pclk;
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} irq;
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};
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static inline struct nv50_display *
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nv50_display(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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return dev_priv->engine.display.priv;
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}
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int nv50_display_early_init(struct drm_device *dev);
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void nv50_display_late_takedown(struct drm_device *dev);
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int nv50_display_create(struct drm_device *dev);
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int nv50_display_init(struct drm_device *dev);
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void nv50_display_fini(struct drm_device *dev);
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void nv50_display_destroy(struct drm_device *dev);
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int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
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int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
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u32 nv50_display_active_crtcs(struct drm_device *);
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int nv50_display_sync(struct drm_device *);
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int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
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struct nouveau_channel *chan);
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void nv50_display_flip_stop(struct drm_crtc *);
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int nv50_evo_create(struct drm_device *dev);
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void nv50_evo_destroy(struct drm_device *dev);
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int nv50_evo_init(struct drm_device *dev);
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void nv50_evo_fini(struct drm_device *dev);
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void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base,
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u64 size);
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int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 handle, u32 memtype,
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u64 base, u64 size, struct nouveau_gpuobj **);
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#endif /* __NV50_DISPLAY_H__ */
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