Tomasz Figa 86576fbe20 clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider ... The clock was missing CLK_SET_RATE_PARENT flag, which caused rate setting failures due to inability of reconfiguration of second divider behind it. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>		2013-12-21 07:58:38 +09:00
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clk-exynos-audss.c	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
clk-exynos4.c	clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider	2013-12-21 07:58:38 +09:00
clk-exynos5250.c	clk: samsung: exynos5250: Simplify registration of PLL rate tables	2013-09-06 13:34:05 -07:00
clk-exynos5420.c	clk/exynos5420: assign dout_pixel id to pixel clock divider	2013-08-29 17:48:12 -07:00
clk-exynos5440.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk-pll.c	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-pll.h	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-s3c64xx.c	clk: s3c64xx: Fix incorrect placement of __initdata	2013-08-27 18:36:20 -07:00
clk.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk.h	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
Makefile	ARM: S3C64XX: Migrate clock handling to Common Clock Framework	2013-09-17 06:47:36 +09:00