f229006ec6
Fix irq_set_affinity callbacks in the Meta IRQ chip drivers to AND cpu_online_mask into the cpumask when picking a CPU to vector the interrupt to. As Thomas pointed out, the /proc/irq/$N/smp_affinity interface doesn't filter out offline CPUs, so without this patch if you offline CPU0 and set an IRQ affinity to 0x3 it vectors the interrupt onto CPU0 even though it is offline. Reported-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-metag@vger.kernel.org Cc: stable@vger.kernel.org
343 lines
9.4 KiB
C
343 lines
9.4 KiB
C
/*
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* Meta internal (HWSTATMETA) interrupt code.
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*
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* Copyright (C) 2011-2012 Imagination Technologies Ltd.
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*
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* This code is based on the code in SoC/common/irq.c and SoC/comet/irq.c
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* The code base could be generalised/merged as a lot of the functionality is
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* similar. Until this is done, we try to keep the code simple here.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <asm/irq.h>
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#include <asm/hwthread.h>
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#define PERF0VECINT 0x04820580
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#define PERF1VECINT 0x04820588
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#define PERF0TRIG_OFFSET 16
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#define PERF1TRIG_OFFSET 17
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/**
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* struct metag_internal_irq_priv - private meta internal interrupt data
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* @domain: IRQ domain for all internal Meta IRQs (HWSTATMETA)
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* @unmasked: Record of unmasked IRQs
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*/
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struct metag_internal_irq_priv {
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struct irq_domain *domain;
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unsigned long unmasked;
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};
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/* Private data for the one and only internal interrupt controller */
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static struct metag_internal_irq_priv metag_internal_irq_priv;
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static unsigned int metag_internal_irq_startup(struct irq_data *data);
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static void metag_internal_irq_shutdown(struct irq_data *data);
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static void metag_internal_irq_ack(struct irq_data *data);
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static void metag_internal_irq_mask(struct irq_data *data);
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static void metag_internal_irq_unmask(struct irq_data *data);
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#ifdef CONFIG_SMP
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static int metag_internal_irq_set_affinity(struct irq_data *data,
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const struct cpumask *cpumask, bool force);
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#endif
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static struct irq_chip internal_irq_edge_chip = {
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.name = "HWSTATMETA-IRQ",
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.irq_startup = metag_internal_irq_startup,
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.irq_shutdown = metag_internal_irq_shutdown,
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.irq_ack = metag_internal_irq_ack,
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.irq_mask = metag_internal_irq_mask,
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.irq_unmask = metag_internal_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = metag_internal_irq_set_affinity,
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#endif
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};
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/*
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* metag_hwvec_addr - get the address of *VECINT regs of irq
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*
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* This function is a table of supported triggers on HWSTATMETA
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* Could do with a structure, but better keep it simple. Changes
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* in this code should be rare.
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*/
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static inline void __iomem *metag_hwvec_addr(irq_hw_number_t hw)
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{
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void __iomem *addr;
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switch (hw) {
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case PERF0TRIG_OFFSET:
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addr = (void __iomem *)PERF0VECINT;
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break;
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case PERF1TRIG_OFFSET:
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addr = (void __iomem *)PERF1VECINT;
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break;
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default:
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addr = NULL;
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break;
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}
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return addr;
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}
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/*
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* metag_internal_startup - setup an internal irq
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* @irq: the irq to startup
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*
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* Multiplex interrupts for @irq onto TR1. Clear any pending
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* interrupts.
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*/
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static unsigned int metag_internal_irq_startup(struct irq_data *data)
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{
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/* Clear (toggle) the bit in HWSTATMETA for our interrupt. */
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metag_internal_irq_ack(data);
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/* Enable the interrupt by unmasking it */
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metag_internal_irq_unmask(data);
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return 0;
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}
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/*
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* metag_internal_irq_shutdown - turn off the irq
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* @irq: the irq number to turn off
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*
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* Mask @irq and clear any pending interrupts.
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* Stop muxing @irq onto TR1.
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*/
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static void metag_internal_irq_shutdown(struct irq_data *data)
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{
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/* Disable the IRQ at the core by masking it. */
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metag_internal_irq_mask(data);
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/* Clear (toggle) the bit in HWSTATMETA for our interrupt. */
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metag_internal_irq_ack(data);
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}
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/*
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* metag_internal_irq_ack - acknowledge irq
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* @irq: the irq to ack
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*/
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static void metag_internal_irq_ack(struct irq_data *data)
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{
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irq_hw_number_t hw = data->hwirq;
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unsigned int bit = 1 << hw;
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if (metag_in32(HWSTATMETA) & bit)
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metag_out32(bit, HWSTATMETA);
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}
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/**
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* metag_internal_irq_mask() - mask an internal irq by unvectoring
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* @data: data for the internal irq to mask
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*
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* HWSTATMETA has no mask register. Instead the IRQ is unvectored from the core
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* and retriggered if necessary later.
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*/
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static void metag_internal_irq_mask(struct irq_data *data)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
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irq_hw_number_t hw = data->hwirq;
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void __iomem *vec_addr = metag_hwvec_addr(hw);
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clear_bit(hw, &priv->unmasked);
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/* there is no interrupt mask, so unvector the interrupt */
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metag_out32(0, vec_addr);
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}
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/**
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* meta_intc_unmask_edge_irq_nomask() - unmask an edge irq by revectoring
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* @data: data for the internal irq to unmask
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*
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* HWSTATMETA has no mask register. Instead the IRQ is revectored back to the
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* core and retriggered if necessary.
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*/
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static void metag_internal_irq_unmask(struct irq_data *data)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
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irq_hw_number_t hw = data->hwirq;
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unsigned int bit = 1 << hw;
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void __iomem *vec_addr = metag_hwvec_addr(hw);
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unsigned int thread = hard_processor_id();
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set_bit(hw, &priv->unmasked);
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/* there is no interrupt mask, so revector the interrupt */
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metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR1(thread)), vec_addr);
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/*
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* Re-trigger interrupt
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*
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* Writing a 1 toggles, and a 0->1 transition triggers. We only
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* retrigger if the status bit is already set, which means we
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* need to clear it first. Retriggering is fundamentally racy
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* because if the interrupt fires again after we clear it we
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* could end up clearing it again and the interrupt handler
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* thinking it hasn't fired. Therefore we need to keep trying to
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* retrigger until the bit is set.
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*/
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if (metag_in32(HWSTATMETA) & bit) {
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metag_out32(bit, HWSTATMETA);
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while (!(metag_in32(HWSTATMETA) & bit))
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metag_out32(bit, HWSTATMETA);
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}
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}
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#ifdef CONFIG_SMP
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/*
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* metag_internal_irq_set_affinity - set the affinity for an interrupt
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*/
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static int metag_internal_irq_set_affinity(struct irq_data *data,
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const struct cpumask *cpumask, bool force)
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{
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unsigned int cpu, thread;
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irq_hw_number_t hw = data->hwirq;
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/*
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* Wire up this interrupt from *VECINT to the Meta core.
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*
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* Note that we can't wire up *VECINT to interrupt more than
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* one cpu (the interrupt code doesn't support it), so we just
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* pick the first cpu we find in 'cpumask'.
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*/
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cpu = cpumask_any_and(cpumask, cpu_online_mask);
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thread = cpu_2_hwthread_id[cpu];
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metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR1(thread)),
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metag_hwvec_addr(hw));
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return 0;
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}
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#endif
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/*
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* metag_internal_irq_demux - irq de-multiplexer
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* @irq: the interrupt number
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* @desc: the interrupt description structure for this irq
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*
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* The cpu receives an interrupt on TR1 when an interrupt has
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* occurred. It is this function's job to demux this irq and
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* figure out exactly which trigger needs servicing.
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*/
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static void metag_internal_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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struct metag_internal_irq_priv *priv = irq_desc_get_handler_data(desc);
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irq_hw_number_t hw;
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unsigned int irq_no;
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u32 status;
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recalculate:
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status = metag_in32(HWSTATMETA) & priv->unmasked;
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for (hw = 0; status != 0; status >>= 1, ++hw) {
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if (status & 0x1) {
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/*
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* Map the hardware IRQ number to a virtual Linux IRQ
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* number.
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*/
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irq_no = irq_linear_revmap(priv->domain, hw);
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/*
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* Only fire off interrupts that are
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* registered to be handled by the kernel.
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* Other interrupts are probably being
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* handled by other Meta hardware threads.
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*/
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generic_handle_irq(irq_no);
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/*
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* The handler may have re-enabled interrupts
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* which could have caused a nested invocation
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* of this code and make the copy of the
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* status register we are using invalid.
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*/
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goto recalculate;
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}
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}
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}
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/**
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* internal_irq_map() - Map an internal meta IRQ to a virtual IRQ number.
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* @hw: Number of the internal IRQ. Must be in range.
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*
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* Returns: The virtual IRQ number of the Meta internal IRQ specified by
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* @hw.
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*/
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int internal_irq_map(unsigned int hw)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
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if (!priv->domain)
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return -ENODEV;
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return irq_create_mapping(priv->domain, hw);
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}
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/**
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* metag_internal_irq_init_cpu - regsister with the Meta cpu
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* @cpu: the CPU to register on
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*
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* Configure @cpu's TR1 irq so that we can demux irqs.
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*/
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static void metag_internal_irq_init_cpu(struct metag_internal_irq_priv *priv,
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int cpu)
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{
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unsigned int thread = cpu_2_hwthread_id[cpu];
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unsigned int signum = TBID_SIGNUM_TR1(thread);
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int irq = tbisig_map(signum);
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/* Register the multiplexed IRQ handler */
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irq_set_handler_data(irq, priv);
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irq_set_chained_handler(irq, metag_internal_irq_demux);
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irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
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}
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/**
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* metag_internal_intc_map() - map an internal irq
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* @d: irq domain of internal trigger block
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* @irq: virtual irq number
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* @hw: hardware irq number within internal trigger block
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*
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* This sets up a virtual irq for a specified hardware interrupt. The irq chip
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* and handler is configured.
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*/
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static int metag_internal_intc_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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/* only register interrupt if it is mapped */
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if (!metag_hwvec_addr(hw))
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return -EINVAL;
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irq_set_chip_and_handler(irq, &internal_irq_edge_chip,
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handle_edge_irq);
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return 0;
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}
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static const struct irq_domain_ops metag_internal_intc_domain_ops = {
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.map = metag_internal_intc_map,
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};
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/**
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* metag_internal_irq_register - register internal IRQs
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*
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* Register the irq chip and handler function for all internal IRQs
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*/
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int __init init_internal_IRQ(void)
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{
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struct metag_internal_irq_priv *priv = &metag_internal_irq_priv;
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unsigned int cpu;
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/* Set up an IRQ domain */
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priv->domain = irq_domain_add_linear(NULL, 32,
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&metag_internal_intc_domain_ops,
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priv);
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if (unlikely(!priv->domain)) {
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pr_err("meta-internal-intc: cannot add IRQ domain\n");
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return -ENOMEM;
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}
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/* Setup TR1 for all cpus. */
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for_each_possible_cpu(cpu)
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metag_internal_irq_init_cpu(priv, cpu);
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return 0;
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};
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