9c39fc1fe8
Fix parent of EMAC and voice codec PSC clocks. Documentation is clear on EMAC clock parent, but its not fully clear on parent of voice codec clock. The implementation chosen is matches arch/arm/mach-davinci/dm365.c. Add a comment explaining this for posterity. There is only one power domain on DM365. Fix the power domain of voice codec and vpss dac modules. While at it, add a comment explaining how the parent of vpss dac clock was derived. Note that this patch does not touch the parent of vpss dac clock. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180525181150.17873-6-david@lechnology.com
109 lines
4.7 KiB
C
109 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PSC clock descriptions for TI DaVinci DM365
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include "psc.h"
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LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
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LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
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LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
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LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp");
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LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
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LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
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LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL);
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LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
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LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
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LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
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LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
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LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
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/* REVISIT: gpio-davinci.c should be modified to drop con_id */
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LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
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LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
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LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
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LPSC_CLKDEV1(spi3_clkdev, NULL, "spi_davinci.3");
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LPSC_CLKDEV1(spi4_clkdev, NULL, "spi_davinci.4");
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LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
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"fck", "davinci_mdio.0");
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LPSC_CLKDEV1(voice_codec_clkdev, NULL, "davinci_voicecodec");
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LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
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LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
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static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
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LPSC(1, 0, vpss_slave, pll1_sysclk5, vpss_slave_clkdev, 0),
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LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
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LPSC(6, 0, spi1, pll1_sysclk4, spi1_clkdev, 0),
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LPSC(7, 0, mmcsd1, pll1_sysclk4, mmcsd1_clkdev, 0),
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LPSC(8, 0, asp0, pll1_sysclk4, asp0_clkdev, 0),
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LPSC(9, 0, usb, pll1_auxclk, usb_clkdev, 0),
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LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
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LPSC(11, 0, spi2, pll1_sysclk4, spi2_clkdev, 0),
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LPSC(12, 0, rto, pll1_sysclk4, NULL, 0),
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LPSC(14, 0, aemif, pll1_sysclk4, aemif_clkdev, 0),
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LPSC(15, 0, mmcsd0, pll1_sysclk8, mmcsd0_clkdev, 0),
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LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
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LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
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LPSC(20, 0, uart1, pll1_sysclk4, uart1_clkdev, 0),
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LPSC(22, 0, spi0, pll1_sysclk4, spi0_clkdev, 0),
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LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
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LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
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LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
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LPSC(26, 0, gpio, pll1_sysclk4, gpio_clkdev, 0),
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LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
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LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
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/* REVISIT: why can't this be disabled? */
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LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
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LPSC(31, 0, arm, pll2_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(38, 0, spi3, pll1_sysclk4, spi3_clkdev, 0),
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LPSC(39, 0, spi4, pll1_auxclk, spi4_clkdev, 0),
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LPSC(40, 0, emac, pll1_sysclk4, emac_clkdev, 0),
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/*
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* The TRM (ARM Subsystem User's Guide) shows two clocks input into
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* voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
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* not fully clear from documentation which clock should be considered
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* as parent for PSC. The clock chosen here is to maintain
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* compatibility with existing code in arch/arm/mach-davinci/dm365.c
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*/
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LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
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/*
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* Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
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* the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
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* into HDVICP and MJCP. The clock chosen here is to remain compatible
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* with code existing in arch/arm/mach-davinci/dm365.c
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*/
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LPSC(46, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
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LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
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LPSC(50, 0, mjcp, pll1_sysclk3, NULL, 0),
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{ }
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};
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static int dm365_psc_init(struct device *dev, void __iomem *base)
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{
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return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
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}
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static struct clk_bulk_data dm365_psc_parent_clks[] = {
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{ .id = "pll1_sysclk1" },
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{ .id = "pll1_sysclk3" },
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{ .id = "pll1_sysclk4" },
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{ .id = "pll1_sysclk5" },
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{ .id = "pll1_sysclk8" },
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{ .id = "pll2_sysclk2" },
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{ .id = "pll2_sysclk4" },
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{ .id = "pll1_auxclk" },
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};
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const struct davinci_psc_init_data dm365_psc_init_data = {
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.parent_clks = dm365_psc_parent_clks,
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.num_parent_clks = ARRAY_SIZE(dm365_psc_parent_clks),
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.psc_init = &dm365_psc_init,
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};
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