61fbb1d278
The three SoCs share a common clock tree which only differs in the existence of some special clocks. As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
92 lines
2.2 KiB
C
92 lines
2.2 KiB
C
/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants clock controllers of Samsung S3C2443 and later.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
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#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
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/*
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* Let each exported clock get a unique index, which is used on DT-enabled
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* platforms to lookup the clock from a clock specifier. These indices are
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* therefore considered an ABI and so must not be changed. This implies
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* that new clocks should be added either in free spaces between clock groups
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* or at the end.
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*/
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/* Core clocks. */
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#define MSYSCLK 1
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#define ESYSCLK 2
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#define ARMDIV 3
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#define ARMCLK 4
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#define HCLK 5
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#define PCLK 6
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/* Special clocks */
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#define SCLK_HSSPI0 16
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#define SCLK_FIMD 17
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#define SCLK_I2S0 18
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#define SCLK_I2S1 19
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#define SCLK_HSMMC1 20
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#define SCLK_HSMMC_EXT 21
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#define SCLK_CAM 22
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#define SCLK_UART 23
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#define SCLK_USBH 24
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/* Muxes */
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#define MUX_HSSPI0 32
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#define MUX_HSSPI1 33
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#define MUX_HSMMC0 34
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#define MUX_HSMMC1 35
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/* hclk-gates */
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#define HCLK_DMA0 48
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#define HCLK_DMA1 49
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#define HCLK_DMA2 50
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#define HCLK_DMA3 51
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#define HCLK_DMA4 52
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#define HCLK_DMA5 53
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#define HCLK_DMA6 54
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#define HCLK_DMA7 55
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#define HCLK_CAM 56
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#define HCLK_LCD 57
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#define HCLK_USBH 58
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#define HCLK_USBD 59
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#define HCLK_IROM 60
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#define HCLK_HSMMC0 61
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#define HCLK_HSMMC1 62
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#define HCLK_CFC 63
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#define HCLK_SSMC 64
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#define HCLK_DRAM 65
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#define HCLK_2D 66
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/* pclk-gates */
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#define PCLK_UART0 72
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#define PCLK_UART1 73
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#define PCLK_UART2 74
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#define PCLK_UART3 75
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#define PCLK_I2C0 76
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#define PCLK_SDI 77
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#define PCLK_SPI0 78
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#define PCLK_ADC 79
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#define PCLK_AC97 80
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#define PCLK_I2S0 81
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#define PCLK_PWM 82
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#define PCLK_WDT 83
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#define PCLK_RTC 84
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#define PCLK_GPIO 85
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#define PCLK_SPI1 86
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#define PCLK_CHIPID 87
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#define PCLK_I2C1 88
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#define PCLK_I2S1 89
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#define PCLK_PCM 90
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/* Total number of clocks. */
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#define NR_CLKS (PCLK_PCM + 1)
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#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
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