6784fd5931
Fix the FRV cmpxchg_local by breaking the following header dependency loop : linux/kernel.h -> linux/bitops.h -> asm-frv/bitops.h -> asm-frv/atomic.h -> asm-frv/system.h -> asm-generic/cmpxchg_local.h -> typecheck() defined in linux/kernel.h and linux/kernel.h -> linux/bitops.h -> asm-frv/bitops.h -> asm-frv/atomic.h -> asm-generic/cmpxchg_local.h -> typecheck() defined in linux/kernel.h In order to fix this : - Move the atomic_test_and_ *_mask inlines from asm-frv/atomic.h (why are they there at all anyway ? They are not touching atomic_t variables!) to asm-frv/bitops.h. Also fix a build issue with cmpxchg : it does not cast to (unsigned long *) like other architectures, to deal with it in the cmpxchg_local macro. FRV builds fine with this patch. Thanks to Adrian Bunk <bunk@kernel.org> for spotting this bug. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Cc: Adrian Bunk <bunk@kernel.org> Cc: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
399 lines
9.3 KiB
C
399 lines
9.3 KiB
C
/* bitops.h: bit operations for the Fujitsu FR-V CPUs
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*
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* For an explanation of how atomic ops work in this arch, see:
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* Documentation/frv/atomic-ops.txt
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_BITOPS_H
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#define _ASM_BITOPS_H
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#include <linux/compiler.h>
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#include <asm/byteorder.h>
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#ifdef __KERNEL__
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <asm-generic/bitops/ffz.h>
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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static inline
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unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
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{
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unsigned long old, tmp;
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asm volatile(
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"0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" and%I3 %1,%3,%2 \n"
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" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
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" beq icc3,#0,0b \n"
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: "+U"(*v), "=&r"(old), "=r"(tmp)
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: "NPr"(~mask)
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: "memory", "cc7", "cc3", "icc3"
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);
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return old;
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}
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static inline
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unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
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{
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unsigned long old, tmp;
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asm volatile(
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"0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" or%I3 %1,%3,%2 \n"
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" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
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" beq icc3,#0,0b \n"
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: "+U"(*v), "=&r"(old), "=r"(tmp)
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: "NPr"(mask)
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: "memory", "cc7", "cc3", "icc3"
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);
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return old;
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}
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static inline
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unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
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{
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unsigned long old, tmp;
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asm volatile(
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"0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" xor%I3 %1,%3,%2 \n"
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" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
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" beq icc3,#0,0b \n"
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: "+U"(*v), "=&r"(old), "=r"(tmp)
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: "NPr"(mask)
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: "memory", "cc7", "cc3", "icc3"
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);
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return old;
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}
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#else
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extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
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extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
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extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
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#endif
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#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
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#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
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static inline int test_and_clear_bit(int nr, volatile void *addr)
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{
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volatile unsigned long *ptr = addr;
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unsigned long mask = 1UL << (nr & 31);
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ptr += nr >> 5;
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return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0;
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}
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static inline int test_and_set_bit(int nr, volatile void *addr)
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{
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volatile unsigned long *ptr = addr;
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unsigned long mask = 1UL << (nr & 31);
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ptr += nr >> 5;
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return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0;
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}
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static inline int test_and_change_bit(int nr, volatile void *addr)
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{
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volatile unsigned long *ptr = addr;
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unsigned long mask = 1UL << (nr & 31);
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ptr += nr >> 5;
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return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0;
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}
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static inline void clear_bit(int nr, volatile void *addr)
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{
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test_and_clear_bit(nr, addr);
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}
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static inline void set_bit(int nr, volatile void *addr)
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{
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test_and_set_bit(nr, addr);
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}
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static inline void change_bit(int nr, volatile void * addr)
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{
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test_and_change_bit(nr, addr);
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}
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static inline void __clear_bit(int nr, volatile void * addr)
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{
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volatile unsigned long *a = addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 31);
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*a &= ~mask;
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}
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static inline void __set_bit(int nr, volatile void * addr)
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{
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volatile unsigned long *a = addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 31);
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*a |= mask;
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}
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static inline void __change_bit(int nr, volatile void *addr)
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{
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volatile unsigned long *a = addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 31);
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*a ^= mask;
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}
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static inline int __test_and_clear_bit(int nr, volatile void * addr)
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{
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volatile unsigned long *a = addr;
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int mask, retval;
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a += nr >> 5;
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mask = 1 << (nr & 31);
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retval = (mask & *a) != 0;
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*a &= ~mask;
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return retval;
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}
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static inline int __test_and_set_bit(int nr, volatile void * addr)
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{
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volatile unsigned long *a = addr;
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int mask, retval;
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a += nr >> 5;
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mask = 1 << (nr & 31);
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retval = (mask & *a) != 0;
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*a |= mask;
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return retval;
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}
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static inline int __test_and_change_bit(int nr, volatile void * addr)
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{
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volatile unsigned long *a = addr;
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int mask, retval;
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a += nr >> 5;
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mask = 1 << (nr & 31);
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retval = (mask & *a) != 0;
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*a ^= mask;
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return retval;
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}
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/*
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* This routine doesn't need to be atomic.
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*/
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static inline int __constant_test_bit(int nr, const volatile void * addr)
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{
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return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
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}
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static inline int __test_bit(int nr, const volatile void * addr)
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{
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int * a = (int *) addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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return ((mask & *a) != 0);
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}
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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__constant_test_bit((nr),(addr)) : \
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__test_bit((nr),(addr)))
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#include <asm-generic/bitops/find.h>
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/**
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* fls - find last bit set
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* @x: the word to search
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*
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* This is defined the same way as ffs:
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* - return 32..1 to indicate bit 31..0 most significant bit set
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* - return 0 to indicate no bits set
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*/
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#define fls(x) \
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({ \
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int bit; \
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\
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asm(" subcc %1,gr0,gr0,icc0 \n" \
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" ckne icc0,cc4 \n" \
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" cscan.p %1,gr0,%0 ,cc4,#1 \n" \
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" csub %0,%0,%0 ,cc4,#0 \n" \
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" csub %2,%0,%0 ,cc4,#1 \n" \
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: "=&r"(bit) \
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: "r"(x), "r"(32) \
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: "icc0", "cc4" \
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); \
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\
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bit; \
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})
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/**
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* fls64 - find last bit set in a 64-bit value
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* @n: the value to search
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*
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* This is defined the same way as ffs:
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* - return 64..1 to indicate bit 63..0 most significant bit set
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* - return 0 to indicate no bits set
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*/
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static inline __attribute__((const))
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int fls64(u64 n)
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{
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union {
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u64 ll;
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struct { u32 h, l; };
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} _;
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int bit, x, y;
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_.ll = n;
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asm(" subcc.p %3,gr0,gr0,icc0 \n"
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" subcc %4,gr0,gr0,icc1 \n"
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" ckne icc0,cc4 \n"
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" ckne icc1,cc5 \n"
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" norcr cc4,cc5,cc6 \n"
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" csub.p %0,%0,%0 ,cc6,1 \n"
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" orcr cc5,cc4,cc4 \n"
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" andcr cc4,cc5,cc4 \n"
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" cscan.p %3,gr0,%0 ,cc4,0 \n"
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" setlos #64,%1 \n"
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" cscan.p %4,gr0,%0 ,cc4,1 \n"
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" setlos #32,%2 \n"
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" csub.p %1,%0,%0 ,cc4,0 \n"
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" csub %2,%0,%0 ,cc4,1 \n"
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: "=&r"(bit), "=r"(x), "=r"(y)
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: "0r"(_.h), "r"(_.l)
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: "icc0", "icc1", "cc4", "cc5", "cc6"
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);
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return bit;
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}
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/**
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* ffs - find first bit set
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* @x: the word to search
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*
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* - return 32..1 to indicate bit 31..0 most least significant bit set
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* - return 0 to indicate no bits set
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*/
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static inline __attribute__((const))
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int ffs(int x)
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{
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/* Note: (x & -x) gives us a mask that is the least significant
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* (rightmost) 1-bit of the value in x.
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*/
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return fls(x & -x);
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}
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/**
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* __ffs - find first bit set
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* @x: the word to search
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*
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* - return 31..0 to indicate bit 31..0 most least significant bit set
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* - if no bits are set in x, the result is undefined
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*/
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static inline __attribute__((const))
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int __ffs(unsigned long x)
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{
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int bit;
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asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
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return 31 - bit;
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}
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/*
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* special slimline version of fls() for calculating ilog2_u32()
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* - note: no protection against n == 0
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*/
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#define ARCH_HAS_ILOG2_U32
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static inline __attribute__((const))
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int __ilog2_u32(u32 n)
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{
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int bit;
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asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
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return 31 - bit;
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}
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/*
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* special slimline version of fls64() for calculating ilog2_u64()
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* - note: no protection against n == 0
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*/
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#define ARCH_HAS_ILOG2_U64
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static inline __attribute__((const))
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int __ilog2_u64(u64 n)
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{
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union {
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u64 ll;
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struct { u32 h, l; };
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} _;
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int bit, x, y;
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_.ll = n;
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asm(" subcc %3,gr0,gr0,icc0 \n"
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" ckeq icc0,cc4 \n"
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" cscan.p %3,gr0,%0 ,cc4,0 \n"
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" setlos #63,%1 \n"
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" cscan.p %4,gr0,%0 ,cc4,1 \n"
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" setlos #31,%2 \n"
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" csub.p %1,%0,%0 ,cc4,0 \n"
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" csub %2,%0,%0 ,cc4,1 \n"
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: "=&r"(bit), "=r"(x), "=r"(y)
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: "0r"(_.h), "r"(_.l)
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: "icc0", "cc4"
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);
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return bit;
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}
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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#include <asm-generic/bitops/ext2-non-atomic.h>
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#define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit ((nr) ^ 0x18, (addr))
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#define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr) ^ 0x18, (addr))
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#include <asm-generic/bitops/minix-le.h>
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#endif /* __KERNEL__ */
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#endif /* _ASM_BITOPS_H */
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