af47e6bb88
Introduce an IP reset API for use on DaVinci SoC. There is no existing "reset" framework support for SoC devices. The remoteproc driver needs explicit control of the DSP's reset line. To support this, a new DaVinci specific API is added. This private API will disappear with DT migration. Some discussion regarding a proposed DT "reset" binding is here: https://patchwork.kernel.org/patch/1635051/ Modify davinci_clk_init() to set clk "reset" function for clocks that indicate PSC_LRST support. Also fix indentation issue with function opening curly brace. Signed-off-by: Robert Tivy <rtivy@ti.com> [nsekhar@ti.com: rename davinci_psc_config_reset() to davinci_psc_reset()] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* TI DaVinci Power and Sleep Controller (PSC)
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/cputype.h>
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#include <mach/psc.h>
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#include "clock.h"
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/* Return nonzero iff the domain's clock is active */
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int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
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{
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void __iomem *psc_base;
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u32 mdstat;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
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pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
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(int)soc_info->psc_bases, ctlr);
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return 0;
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}
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psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
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mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
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iounmap(psc_base);
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/* if clocked, state can be "Enable" or "SyncReset" */
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return mdstat & BIT(12);
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}
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/* Control "reset" line associated with PSC domain */
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void davinci_psc_reset(unsigned int ctlr, unsigned int id, bool reset)
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{
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u32 mdctl;
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void __iomem *psc_base;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
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pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
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(int)soc_info->psc_bases, ctlr);
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return;
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}
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psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
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mdctl = readl(psc_base + MDCTL + 4 * id);
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if (reset)
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mdctl &= ~MDCTL_LRST;
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else
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mdctl |= MDCTL_LRST;
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writel(mdctl, psc_base + MDCTL + 4 * id);
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iounmap(psc_base);
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}
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/* Enable or disable a PSC domain */
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void davinci_psc_config(unsigned int domain, unsigned int ctlr,
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unsigned int id, bool enable, u32 flags)
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{
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u32 epcpr, ptcmd, ptstat, pdstat, pdctl, mdstat, mdctl;
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void __iomem *psc_base;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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u32 next_state = PSC_STATE_ENABLE;
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if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
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pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
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(int)soc_info->psc_bases, ctlr);
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return;
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}
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psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
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if (!enable) {
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if (flags & PSC_SWRSTDISABLE)
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next_state = PSC_STATE_SWRSTDISABLE;
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else
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next_state = PSC_STATE_DISABLE;
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}
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mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
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mdctl &= ~MDSTAT_STATE_MASK;
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mdctl |= next_state;
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if (flags & PSC_FORCE)
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mdctl |= MDCTL_FORCE;
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__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
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pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain);
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if ((pdstat & PDSTAT_STATE_MASK) == 0) {
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pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
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pdctl |= PDCTL_NEXT;
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__raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
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ptcmd = 1 << domain;
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__raw_writel(ptcmd, psc_base + PTCMD);
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do {
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epcpr = __raw_readl(psc_base + EPCPR);
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} while ((((epcpr >> domain) & 1) == 0));
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pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
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pdctl |= PDCTL_EPCGOOD;
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__raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
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} else {
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ptcmd = 1 << domain;
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__raw_writel(ptcmd, psc_base + PTCMD);
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}
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do {
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ptstat = __raw_readl(psc_base + PTSTAT);
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} while (!(((ptstat >> domain) & 1) == 0));
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do {
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mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
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} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
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iounmap(psc_base);
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}
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