bab588fcfb
This is a larger set of new functionality for the existing SoC families,
including:
* vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850
* prima2 gains support for the "marco" SoC family, its SMP based cousin
* tegra gains support for the new Tegra4 (Tegra114) family
* socfpga now supports a newer version of the hardware including SMP
* i.mx31 and bcm2835 are now using DT probing for their clocks
* lots of updates for sh-mobile
* OMAP updates for clocks, power management and USB
* i.mx6q and tegra now support cpuidle
* kirkwood now supports PCIe hot plugging
* tegra clock support is updated
* tegra USB PHY probing gets implemented diffently
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann:
"This is a larger set of new functionality for the existing SoC
families, including:
- vt8500 gains support for new CPU cores, notably the Cortex-A9 based
wm8850
- prima2 gains support for the "marco" SoC family, its SMP based
cousin
- tegra gains support for the new Tegra4 (Tegra114) family
- socfpga now supports a newer version of the hardware including SMP
- i.mx31 and bcm2835 are now using DT probing for their clocks
- lots of updates for sh-mobile
- OMAP updates for clocks, power management and USB
- i.mx6q and tegra now support cpuidle
- kirkwood now supports PCIe hot plugging
- tegra clock support is updated
- tegra USB PHY probing gets implemented diffently"
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
ARM: prima2: remove duplicate v7_invalidate_l1
ARM: shmobile: r8a7779: Correct TMU clock support again
ARM: prima2: fix __init section for cpu hotplug
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
ARM: tegra: Fix build error for gic update
ARM: tegra: remove empty tegra_smp_init_cpus()
ARM: shmobile: Register ARM architected timer
ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
ARM: shmobile: r8a7779: Correct TMU clock support
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
...
97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/*
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* IP block integration code for the HDQ1W/1-wire IP block
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
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* Avinash.H.M <avinashhm@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include "soc.h"
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#include "omap_hwmod.h"
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#include "omap_device.h"
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#include "hdq1w.h"
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#include "prm.h"
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#include "common.h"
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/**
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* omap_hdq1w_reset - reset the OMAP HDQ1W module
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* @oh: struct omap_hwmod *
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*
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* OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
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* Software Reset" of the OMAP34xx Technical Reference Manual Revision
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* ZR (SWPU223R) does not include the rather important fact that, for
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* the reset to succeed, the HDQ1W module's internal clock gate must be
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* programmed to allow the clock to propagate to the rest of the
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* module. In this sense, it's rather similar to the I2C custom reset
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* function. Returns 0.
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*/
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int omap_hdq1w_reset(struct omap_hwmod *oh)
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{
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u32 v;
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int c = 0;
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/* Write to the SOFTRESET bit */
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omap_hwmod_softreset(oh);
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/* Enable the module's internal clocks */
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v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
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v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
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omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
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/* Poll on RESETDONE bit */
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omap_test_timeout((omap_hwmod_read(oh,
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oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warning("%s: %s: softreset failed (waited %d usec)\n",
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__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("%s: %s: softreset in %d usec\n", __func__,
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oh->name, c);
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return 0;
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}
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static int __init omap_init_hdq(void)
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{
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int id = -1;
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struct platform_device *pdev;
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struct omap_hwmod *oh;
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char *oh_name = "hdq1w";
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char *devname = "omap_hdq";
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oh = omap_hwmod_lookup(oh_name);
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if (!oh)
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return 0;
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pdev = omap_device_build(devname, id, oh, NULL, 0);
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WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
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devname, oh->name);
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return 0;
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}
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omap_arch_initcall(omap_init_hdq);
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