linux-hardened/arch/openrisc
Luc Van Oostenryck afa8380881 openrisc: pass endianness info to sparse
openrisc is big-endian only but sparse assumes the same endianness
as the building machine.
This is problematic for code which expect __BYTE_ORDER__ being
correctly predefined by the compiler which sparse can then
pre-process differently from what gcc would, depending on the
building machine endianness.

Fix this by letting sparse know about the architecture endianness.

To: Jonas Bonn <jonas@southpole.se>
To: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
To: Stafford Horne <shorne@gmail.com>
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-11-03 14:01:17 +09:00
..
boot/dts openrisc: add simple_smp dts and defconfig for simulators 2017-11-03 14:01:15 +09:00
configs openrisc: add simple_smp dts and defconfig for simulators 2017-11-03 14:01:15 +09:00
include openrisc: add tick timer multi-core sync logic 2017-11-03 14:01:16 +09:00
kernel openrisc: add tick timer multi-core sync logic 2017-11-03 14:01:16 +09:00
lib openrisc: initial SMP support 2017-11-03 14:01:13 +09:00
mm openrisc: add cacheflush support to fix icache aliasing 2017-11-03 14:01:15 +09:00
Kconfig openrisc: enable LOCKDEP_SUPPORT and irqflags tracing 2017-11-03 14:01:16 +09:00
Makefile openrisc: pass endianness info to sparse 2017-11-03 14:01:17 +09:00