8950778704
Moorestown has PMIC chip which contains GPIO blocks. The PMIC chip is connected to Langwell by SPI interface. So this GPIO driver will be regarded as SPI GPIO expander though the actual GPIO access is through IPC and SRAM. The SPI master contoller will probe this device driver by parsing SPIB table. Cleaned up for new IPC, GPE removed and some printk and other tidying by Alan Cox. Fixes for points noted by Matthew Garrett Signed-off-by: Alek Du <alek.du@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Matthew Garrett <mjg@redhat.com>
15 lines
372 B
C
15 lines
372 B
C
#ifndef LINUX_INTEL_PMIC_H
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#define LINUX_INTEL_PMIC_H
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struct intel_pmic_gpio_platform_data {
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/* the first IRQ of the chip */
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unsigned irq_base;
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/* number assigned to the first GPIO */
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unsigned gpio_base;
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/* sram address for gpiointr register, the langwell chip will map
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* the PMIC spi GPIO expander's GPIOINTR register in sram.
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*/
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unsigned gpiointr;
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};
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#endif
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