1db1af84d6
This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
401 lines
9.1 KiB
C
401 lines
9.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Ralf Baechle
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*/
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#ifndef _ASM_ASMMACRO_H
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#define _ASM_ASMMACRO_H
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#include <asm/hazards.h>
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#ifdef CONFIG_32BIT
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#include <asm/asmmacro-32.h>
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#endif
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#ifdef CONFIG_64BIT
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#include <asm/asmmacro-64.h>
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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.macro local_irq_enable reg=t0
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mfc0 \reg, CP0_TCSTATUS
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ori \reg, \reg, TCSTATUS_IXMT
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xori \reg, \reg, TCSTATUS_IXMT
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mtc0 \reg, CP0_TCSTATUS
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_ehb
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.endm
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.macro local_irq_disable reg=t0
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mfc0 \reg, CP0_TCSTATUS
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ori \reg, \reg, TCSTATUS_IXMT
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mtc0 \reg, CP0_TCSTATUS
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_ehb
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.endm
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#elif defined(CONFIG_CPU_MIPSR2)
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.macro local_irq_enable reg=t0
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ei
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irq_enable_hazard
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.endm
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.macro local_irq_disable reg=t0
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di
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irq_disable_hazard
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.endm
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#else
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.macro local_irq_enable reg=t0
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mfc0 \reg, CP0_STATUS
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ori \reg, \reg, 1
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mtc0 \reg, CP0_STATUS
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irq_enable_hazard
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.endm
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.macro local_irq_disable reg=t0
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mfc0 \reg, CP0_STATUS
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ori \reg, \reg, 1
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xori \reg, \reg, 1
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mtc0 \reg, CP0_STATUS
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irq_disable_hazard
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.endm
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#endif /* CONFIG_MIPS_MT_SMTC */
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.macro fpu_save_16even thread tmp=t0
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cfc1 \tmp, fcr31
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sdc1 $f0, THREAD_FPR0_LS64(\thread)
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sdc1 $f2, THREAD_FPR2_LS64(\thread)
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sdc1 $f4, THREAD_FPR4_LS64(\thread)
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sdc1 $f6, THREAD_FPR6_LS64(\thread)
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sdc1 $f8, THREAD_FPR8_LS64(\thread)
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sdc1 $f10, THREAD_FPR10_LS64(\thread)
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sdc1 $f12, THREAD_FPR12_LS64(\thread)
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sdc1 $f14, THREAD_FPR14_LS64(\thread)
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sdc1 $f16, THREAD_FPR16_LS64(\thread)
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sdc1 $f18, THREAD_FPR18_LS64(\thread)
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sdc1 $f20, THREAD_FPR20_LS64(\thread)
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sdc1 $f22, THREAD_FPR22_LS64(\thread)
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sdc1 $f24, THREAD_FPR24_LS64(\thread)
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sdc1 $f26, THREAD_FPR26_LS64(\thread)
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sdc1 $f28, THREAD_FPR28_LS64(\thread)
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sdc1 $f30, THREAD_FPR30_LS64(\thread)
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sw \tmp, THREAD_FCR31(\thread)
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.endm
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.macro fpu_save_16odd thread
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.set push
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.set mips64r2
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sdc1 $f1, THREAD_FPR1_LS64(\thread)
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sdc1 $f3, THREAD_FPR3_LS64(\thread)
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sdc1 $f5, THREAD_FPR5_LS64(\thread)
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sdc1 $f7, THREAD_FPR7_LS64(\thread)
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sdc1 $f9, THREAD_FPR9_LS64(\thread)
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sdc1 $f11, THREAD_FPR11_LS64(\thread)
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sdc1 $f13, THREAD_FPR13_LS64(\thread)
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sdc1 $f15, THREAD_FPR15_LS64(\thread)
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sdc1 $f17, THREAD_FPR17_LS64(\thread)
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sdc1 $f19, THREAD_FPR19_LS64(\thread)
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sdc1 $f21, THREAD_FPR21_LS64(\thread)
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sdc1 $f23, THREAD_FPR23_LS64(\thread)
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sdc1 $f25, THREAD_FPR25_LS64(\thread)
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sdc1 $f27, THREAD_FPR27_LS64(\thread)
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sdc1 $f29, THREAD_FPR29_LS64(\thread)
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sdc1 $f31, THREAD_FPR31_LS64(\thread)
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.set pop
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.endm
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.macro fpu_save_double thread status tmp
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#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
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sll \tmp, \status, 5
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bgez \tmp, 10f
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fpu_save_16odd \thread
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10:
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#endif
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fpu_save_16even \thread \tmp
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.endm
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.macro fpu_restore_16even thread tmp=t0
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lw \tmp, THREAD_FCR31(\thread)
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ldc1 $f0, THREAD_FPR0_LS64(\thread)
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ldc1 $f2, THREAD_FPR2_LS64(\thread)
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ldc1 $f4, THREAD_FPR4_LS64(\thread)
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ldc1 $f6, THREAD_FPR6_LS64(\thread)
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ldc1 $f8, THREAD_FPR8_LS64(\thread)
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ldc1 $f10, THREAD_FPR10_LS64(\thread)
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ldc1 $f12, THREAD_FPR12_LS64(\thread)
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ldc1 $f14, THREAD_FPR14_LS64(\thread)
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ldc1 $f16, THREAD_FPR16_LS64(\thread)
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ldc1 $f18, THREAD_FPR18_LS64(\thread)
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ldc1 $f20, THREAD_FPR20_LS64(\thread)
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ldc1 $f22, THREAD_FPR22_LS64(\thread)
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ldc1 $f24, THREAD_FPR24_LS64(\thread)
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ldc1 $f26, THREAD_FPR26_LS64(\thread)
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ldc1 $f28, THREAD_FPR28_LS64(\thread)
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ldc1 $f30, THREAD_FPR30_LS64(\thread)
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ctc1 \tmp, fcr31
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.endm
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.macro fpu_restore_16odd thread
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.set push
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.set mips64r2
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ldc1 $f1, THREAD_FPR1_LS64(\thread)
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ldc1 $f3, THREAD_FPR3_LS64(\thread)
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ldc1 $f5, THREAD_FPR5_LS64(\thread)
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ldc1 $f7, THREAD_FPR7_LS64(\thread)
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ldc1 $f9, THREAD_FPR9_LS64(\thread)
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ldc1 $f11, THREAD_FPR11_LS64(\thread)
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ldc1 $f13, THREAD_FPR13_LS64(\thread)
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ldc1 $f15, THREAD_FPR15_LS64(\thread)
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ldc1 $f17, THREAD_FPR17_LS64(\thread)
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ldc1 $f19, THREAD_FPR19_LS64(\thread)
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ldc1 $f21, THREAD_FPR21_LS64(\thread)
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ldc1 $f23, THREAD_FPR23_LS64(\thread)
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ldc1 $f25, THREAD_FPR25_LS64(\thread)
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ldc1 $f27, THREAD_FPR27_LS64(\thread)
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ldc1 $f29, THREAD_FPR29_LS64(\thread)
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ldc1 $f31, THREAD_FPR31_LS64(\thread)
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.set pop
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.endm
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.macro fpu_restore_double thread status tmp
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#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
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sll \tmp, \status, 5
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bgez \tmp, 10f # 16 register mode?
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fpu_restore_16odd \thread
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10:
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#endif
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fpu_restore_16even \thread \tmp
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.endm
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#ifdef CONFIG_CPU_MIPSR2
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.macro _EXT rd, rs, p, s
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ext \rd, \rs, \p, \s
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.endm
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#else /* !CONFIG_CPU_MIPSR2 */
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.macro _EXT rd, rs, p, s
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srl \rd, \rs, \p
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andi \rd, \rd, (1 << \s) - 1
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.endm
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#endif /* !CONFIG_CPU_MIPSR2 */
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/*
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* Temporary until all gas have MT ASE support
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*/
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.macro DMT reg=0
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.word 0x41600bc1 | (\reg << 16)
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.endm
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.macro EMT reg=0
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.word 0x41600be1 | (\reg << 16)
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.endm
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.macro DVPE reg=0
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.word 0x41600001 | (\reg << 16)
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.endm
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.macro EVPE reg=0
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.word 0x41600021 | (\reg << 16)
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.endm
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.macro MFTR rt=0, rd=0, u=0, sel=0
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.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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.macro MTTR rt=0, rd=0, u=0, sel=0
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.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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#ifdef TOOLCHAIN_SUPPORTS_MSA
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.macro ld_d wd, off, base
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.set push
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.set mips32r2
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.set msa
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ld.d $w\wd, \off(\base)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set mips32r2
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.set msa
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st.d $w\wd, \off(\base)
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.set pop
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.endm
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.macro copy_u_w rd, ws, n
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.set push
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.set mips32r2
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.set msa
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copy_u.w \rd, $w\ws[\n]
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.set pop
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.endm
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.macro copy_u_d rd, ws, n
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.set push
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.set mips64r2
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.set msa
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copy_u.d \rd, $w\ws[\n]
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.set pop
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.endm
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.macro insert_w wd, n, rs
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.set push
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.set mips32r2
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.set msa
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insert.w $w\wd[\n], \rs
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.set pop
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.endm
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.macro insert_d wd, n, rs
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.set push
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.set mips64r2
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.set msa
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insert.d $w\wd[\n], \rs
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.set pop
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.endm
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#else
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/*
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* Temporary until all toolchains in use include MSA support.
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*/
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.macro cfcmsa rd, cs
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.set push
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.set noat
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.word 0x787e0059 | (\cs << 11)
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move \rd, $1
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.set pop
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.endm
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.macro ctcmsa cd, rs
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.set push
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.set noat
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move $1, \rs
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.word 0x783e0819 | (\cd << 6)
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.set pop
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.endm
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.macro ld_d wd, off, base
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.set push
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.set noat
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add $1, \base, \off
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.word 0x78000823 | (\wd << 6)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set noat
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add $1, \base, \off
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.word 0x78000827 | (\wd << 6)
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.set pop
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.endm
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.macro copy_u_w rd, ws, n
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.set push
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.set noat
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.word 0x78f00059 | (\n << 16) | (\ws << 11)
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/* move triggers an assembler bug... */
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or \rd, $1, zero
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.set pop
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.endm
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.macro copy_u_d rd, ws, n
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.set push
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.set noat
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.word 0x78f80059 | (\n << 16) | (\ws << 11)
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/* move triggers an assembler bug... */
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or \rd, $1, zero
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.set pop
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.endm
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.macro insert_w wd, n, rs
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.set push
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.set noat
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/* move triggers an assembler bug... */
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or $1, \rs, zero
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.word 0x79300819 | (\n << 16) | (\wd << 6)
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.set pop
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.endm
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.macro insert_d wd, n, rs
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.set push
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.set noat
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/* move triggers an assembler bug... */
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or $1, \rs, zero
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.word 0x79380819 | (\n << 16) | (\wd << 6)
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.set pop
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.endm
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#endif
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.macro msa_save_all thread
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st_d 0, THREAD_FPR0, \thread
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st_d 1, THREAD_FPR1, \thread
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st_d 2, THREAD_FPR2, \thread
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st_d 3, THREAD_FPR3, \thread
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st_d 4, THREAD_FPR4, \thread
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st_d 5, THREAD_FPR5, \thread
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st_d 6, THREAD_FPR6, \thread
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st_d 7, THREAD_FPR7, \thread
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st_d 8, THREAD_FPR8, \thread
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st_d 9, THREAD_FPR9, \thread
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st_d 10, THREAD_FPR10, \thread
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st_d 11, THREAD_FPR11, \thread
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st_d 12, THREAD_FPR12, \thread
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st_d 13, THREAD_FPR13, \thread
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st_d 14, THREAD_FPR14, \thread
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st_d 15, THREAD_FPR15, \thread
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st_d 16, THREAD_FPR16, \thread
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st_d 17, THREAD_FPR17, \thread
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st_d 18, THREAD_FPR18, \thread
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st_d 19, THREAD_FPR19, \thread
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st_d 20, THREAD_FPR20, \thread
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st_d 21, THREAD_FPR21, \thread
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st_d 22, THREAD_FPR22, \thread
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st_d 23, THREAD_FPR23, \thread
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st_d 24, THREAD_FPR24, \thread
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st_d 25, THREAD_FPR25, \thread
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st_d 26, THREAD_FPR26, \thread
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st_d 27, THREAD_FPR27, \thread
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st_d 28, THREAD_FPR28, \thread
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st_d 29, THREAD_FPR29, \thread
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st_d 30, THREAD_FPR30, \thread
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st_d 31, THREAD_FPR31, \thread
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.endm
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.macro msa_restore_all thread
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ld_d 0, THREAD_FPR0, \thread
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ld_d 1, THREAD_FPR1, \thread
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ld_d 2, THREAD_FPR2, \thread
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ld_d 3, THREAD_FPR3, \thread
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ld_d 4, THREAD_FPR4, \thread
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ld_d 5, THREAD_FPR5, \thread
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ld_d 6, THREAD_FPR6, \thread
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ld_d 7, THREAD_FPR7, \thread
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ld_d 8, THREAD_FPR8, \thread
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ld_d 9, THREAD_FPR9, \thread
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ld_d 10, THREAD_FPR10, \thread
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ld_d 11, THREAD_FPR11, \thread
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ld_d 12, THREAD_FPR12, \thread
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ld_d 13, THREAD_FPR13, \thread
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ld_d 14, THREAD_FPR14, \thread
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ld_d 15, THREAD_FPR15, \thread
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ld_d 16, THREAD_FPR16, \thread
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ld_d 17, THREAD_FPR17, \thread
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ld_d 18, THREAD_FPR18, \thread
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ld_d 19, THREAD_FPR19, \thread
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ld_d 20, THREAD_FPR20, \thread
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ld_d 21, THREAD_FPR21, \thread
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ld_d 22, THREAD_FPR22, \thread
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ld_d 23, THREAD_FPR23, \thread
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ld_d 24, THREAD_FPR24, \thread
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ld_d 25, THREAD_FPR25, \thread
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ld_d 26, THREAD_FPR26, \thread
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ld_d 27, THREAD_FPR27, \thread
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ld_d 28, THREAD_FPR28, \thread
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ld_d 29, THREAD_FPR29, \thread
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ld_d 30, THREAD_FPR30, \thread
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ld_d 31, THREAD_FPR31, \thread
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.endm
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#endif /* _ASM_ASMMACRO_H */
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