cc26b3b01b
Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/*
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* linux/arch/arm/mach-omap2/irq.c
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*
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* Interrupt handler for OMAP2 boards.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/mach/irq.h>
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/* selected INTC register offsets */
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#define INTC_REVISION 0x0000
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#define INTC_SYSCONFIG 0x0010
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#define INTC_SYSSTATUS 0x0014
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#define INTC_CONTROL 0x0048
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#define INTC_MIR_CLEAR0 0x0088
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#define INTC_MIR_SET0 0x008c
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#define INTC_PENDING_IRQ0 0x0098
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/* Number of IRQ state bits in each MIR register */
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#define IRQ_BITS_PER_REG 32
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/*
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* OMAP2 has a number of different interrupt controllers, each interrupt
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* controller is identified as its own "bank". Register definitions are
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* fairly consistent for each bank, but not all registers are implemented
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* for each bank.. when in doubt, consult the TRM.
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*/
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static struct omap_irq_bank {
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void __iomem *base_reg;
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unsigned int nr_irqs;
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} __attribute__ ((aligned(4))) irq_banks[] = {
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{
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/* MPU INTC */
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.base_reg = 0,
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.nr_irqs = 96,
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},
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};
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/* INTC bank register get/set */
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static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
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{
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__raw_writel(val, bank->base_reg + reg);
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}
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static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
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{
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return __raw_readl(bank->base_reg + reg);
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}
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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static void omap_ack_irq(unsigned int irq)
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{
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intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
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}
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static void omap_mask_irq(unsigned int irq)
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{
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int offset = irq & (~(IRQ_BITS_PER_REG - 1));
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irq &= (IRQ_BITS_PER_REG - 1);
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intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
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}
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static void omap_unmask_irq(unsigned int irq)
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{
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int offset = irq & (~(IRQ_BITS_PER_REG - 1));
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irq &= (IRQ_BITS_PER_REG - 1);
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intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
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}
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static void omap_mask_ack_irq(unsigned int irq)
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{
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omap_mask_irq(irq);
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omap_ack_irq(irq);
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}
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static struct irq_chip omap_irq_chip = {
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.name = "INTC",
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.ack = omap_mask_ack_irq,
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.mask = omap_mask_irq,
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.unmask = omap_unmask_irq,
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};
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static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
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{
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unsigned long tmp;
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tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
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printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
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"(revision %ld.%ld) with %d interrupts\n",
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bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
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tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
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tmp |= 1 << 1; /* soft reset */
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intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
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while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
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/* Wait for reset to complete */;
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/* Enable autoidle */
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intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
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}
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void __init omap_init_irq(void)
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{
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unsigned long nr_irqs = 0;
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unsigned int nr_banks = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
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struct omap_irq_bank *bank = irq_banks + i;
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if (cpu_is_omap24xx())
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bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
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else if (cpu_is_omap34xx())
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bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
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omap_irq_bank_init_one(bank);
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nr_irqs += bank->nr_irqs;
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nr_banks++;
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}
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printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
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nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
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for (i = 0; i < nr_irqs; i++) {
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set_irq_chip(i, &omap_irq_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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}
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