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linux-hardened/drivers/net/ethernet/chelsio/cxgb4vf
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Hariprasad Shenai ce8f407a3c cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers 
T5 introduces the ability to have separate Packing and Padding Boundaries
for SGE DMA transfers from the chip to Host Memory. This change set takes
advantage of that to set up a smaller Padding Boundary to conserve PCI Link
and Memory Bandwidth with T5.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-11-10 14:15:03 -05:00
..
adapter.h cxgb4vf: Move fl_starv_thres into adapter->sge data structure 2014-11-10 14:15:03 -05:00
cxgb4vf_main.c cxgb4vf: Replace repetitive pci device ID's with right ones 2014-10-29 14:48:12 -04:00
Makefile
sge.c cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers 2014-11-10 14:15:03 -05:00
t4vf_common.h cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers 2014-11-10 14:15:03 -05:00
t4vf_defs.h
t4vf_hw.c cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers 2014-11-10 14:15:03 -05:00