d2d00862df
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose input if not used for memory wait state insertion. The first user will be the OMAP NAND chip to get the NAND read/busy status using gpiolib. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> |
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| .. | ||
| fsl | ||
| ti | ||
| arm,pl172.txt | ||
| ath79-ddr-controller.txt | ||
| calxeda-ddr-ctrlr.txt | ||
| ingenic,jz4780-nemc.txt | ||
| mediatek,smi-common.txt | ||
| mediatek,smi-larb.txt | ||
| mvebu-devbus.txt | ||
| mvebu-sdram-controller.txt | ||
| nvidia,tegra-mc.txt | ||
| omap-gpmc.txt | ||
| renesas,h8300-bsc.txt | ||
| renesas-memory-controllers.txt | ||
| synopsys.txt | ||
| tegra-emc.txt | ||
| ti-aemif.txt | ||