d552920a02
This is a power gating idle mode. It support power gating vdd_cpu rail after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can enter this state only when all secondary CPU is offline. We need to take care and make sure whole secondary CPUs were offline and checking the CPU power gate status. After that, the CPU0 can go into "powered-down" state safely. Then shut off the CPU rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Base on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
104 lines
2.4 KiB
ArmAsm
104 lines
2.4 KiB
ArmAsm
/*
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* arch/arm/mach-tegra/sleep.S
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*
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* Copyright (c) 2010-2011, NVIDIA Corporation.
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* Copyright (c) 2011, Google, Inc.
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*
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* Author: Colin Cross <ccross@android.com>
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* Gary King <gking@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/cache.h>
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#include <asm/cp15.h>
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#include "iomap.h"
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#include "flowctrl.h"
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#include "sleep.h"
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_disable_clean_inv_dcache
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*
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* disable, clean & invalidate the D-cache
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*
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* Corrupted registers: r1-r3, r6, r8, r9-r11
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*/
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ENTRY(tegra_disable_clean_inv_dcache)
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stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
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dmb @ ensure ordering
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/* Disable the D-cache */
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mrc p15, 0, r2, c1, c0, 0
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bic r2, r2, #CR_C
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mcr p15, 0, r2, c1, c0, 0
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isb
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/* Flush the D-cache */
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bl v7_flush_dcache_louis
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/* Trun off coherency */
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exit_smp r4, r5
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ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
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ENDPROC(tegra_disable_clean_inv_dcache)
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/*
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* tegra_sleep_cpu_finish(unsigned long v2p)
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*
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* enters suspend in LP2 by turning off the mmu and jumping to
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* tegra?_tear_down_cpu
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*/
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ENTRY(tegra_sleep_cpu_finish)
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/* Flush and disable the L1 data cache */
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bl tegra_disable_clean_inv_dcache
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mov32 r6, tegra_tear_down_cpu
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ldr r1, [r6]
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add r1, r1, r0
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mov32 r3, tegra_shut_off_mmu
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add r3, r3, r0
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mov r0, r1
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mov pc, r3
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ENDPROC(tegra_sleep_cpu_finish)
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/*
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* tegra_shut_off_mmu
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*
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* r0 = physical address to jump to with mmu off
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*
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* called with VA=PA mapping
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* turns off MMU, icache, dcache and branch prediction
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*/
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.align L1_CACHE_SHIFT
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.pushsection .idmap.text, "ax"
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ENTRY(tegra_shut_off_mmu)
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mrc p15, 0, r3, c1, c0, 0
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movw r2, #CR_I | CR_Z | CR_C | CR_M
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bic r3, r3, r2
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dsb
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mcr p15, 0, r3, c1, c0, 0
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isb
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mov pc, r0
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ENDPROC(tegra_shut_off_mmu)
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.popsection
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#endif
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