e18e2a00ef
This is the long overdue conversion of sparc64 over to the generic IRQ layer. The kernel image is slightly larger, but the BSS is ~60K smaller due to the reduced size of struct ino_bucket. A lot of IRQ implementation details, including ino_bucket, were moved out of asm-sparc64/irq.h and are now private to arch/sparc64/kernel/irq.c, and most of the code in irq.c totally disappeared. One thing that's different at the moment is IRQ distribution, we do it at enable_irq() time. If the cpu mask is ALL then we round-robin using a global rotating cpu counter, else we pick the first cpu in the mask to support single cpu targetting. This is similar to what powerpc's XICS IRQ support code does. This works fine on my UP SB1000, and the SMP build goes fine and runs on that machine, but lots of testing on different setups is needed. Signed-off-by: David S. Miller <davem@davemloft.net>
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
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* irq.h: IRQ registers on the 64-bit Sparc.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#ifndef _SPARC64_IRQ_H
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#define _SPARC64_IRQ_H
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <asm/pil.h>
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#include <asm/ptrace.h>
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/* IMAP/ICLR register defines */
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#define IMAP_VALID 0x80000000 /* IRQ Enabled */
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#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
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#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
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#define IMAP_TID_SHIFT 26
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#define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
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#define IMAP_AID_SHIFT 26
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#define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
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#define IMAP_NID_SHIFT 21
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#define IMAP_IGN 0x000007c0 /* IRQ Group Number */
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#define IMAP_INO 0x0000003f /* IRQ Number */
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#define IMAP_INR 0x000007ff /* Full interrupt number*/
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#define ICLR_IDLE 0x00000000 /* Idle state */
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#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
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#define ICLR_PENDING 0x00000003 /* Pending state */
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/* The largest number of unique interrupt sources we support.
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* If this needs to ever be larger than 255, you need to change
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* the type of ino_bucket->virt_irq as appropriate.
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*
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* ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
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*/
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#define NR_IRQS 255
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extern void irq_install_pre_handler(int virt_irq,
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void (*func)(unsigned int, void *, void *),
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void *arg1, void *arg2);
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#define irq_canonicalize(irq) (irq)
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extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
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extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
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extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
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static __inline__ void set_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%set_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ void clear_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%clear_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ unsigned long get_softint(void)
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{
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unsigned long retval;
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__asm__ __volatile__("rd %%softint, %0"
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: "=r" (retval));
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return retval;
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}
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#endif
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