c658eac628
The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
145 lines
4.2 KiB
C
145 lines
4.2 KiB
C
/*
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* Copyright (c) 2006 Tensilica, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2.1 of the GNU Lesser General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Further, this software is distributed without any warranty that it is
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* free of the rightful claim of any third person regarding infringement
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* or the like. Any license provided herein, whether implied or
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* otherwise, applies only to this software file. Patent licenses, if
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* any, provided herein do not apply to combinations of this program with
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* other software, or any other product whatsoever.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
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* USA.
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*/
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#ifndef _XTENSA_REGS_H
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#define _XTENSA_REGS_H
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/* Special registers. */
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#define LBEG 0
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#define LEND 1
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#define LCOUNT 2
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#define SAR 3
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#define BR 4
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#define SCOMPARE1 12
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#define ACCHI 16
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#define ACCLO 17
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#define MR 32
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#define WINDOWBASE 72
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#define WINDOWSTART 73
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#define PTEVADDR 83
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#define RASID 90
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#define ITLBCFG 91
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#define DTLBCFG 92
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#define IBREAKENABLE 96
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#define DDR 104
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#define IBREAKA 128
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#define DBREAKA 144
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#define DBREAKC 160
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#define EPC 176
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#define EPC_1 177
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#define DEPC 192
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#define EPS 192
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#define EPS_1 193
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#define EXCSAVE 208
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#define EXCSAVE_1 209
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#define INTERRUPT 226
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#define INTENABLE 228
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#define PS 230
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#define THREADPTR 231
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#define EXCCAUSE 232
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#define DEBUGCAUSE 233
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#define CCOUNT 234
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#define PRID 235
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#define ICOUNT 236
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#define ICOUNTLEVEL 237
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#define EXCVADDR 238
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#define CCOMPARE 240
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#define MISC 244
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/* Special names for read-only and write-only interrupt registers. */
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#define INTREAD 226
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#define INTSET 226
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#define INTCLEAR 227
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/* EXCCAUSE register fields */
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#define EXCCAUSE_EXCCAUSE_SHIFT 0
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#define EXCCAUSE_EXCCAUSE_MASK 0x3F
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#define EXCCAUSE_ILLEGAL_INSTRUCTION 0
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#define EXCCAUSE_SYSTEM_CALL 1
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#define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2
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#define EXCCAUSE_LOAD_STORE_ERROR 3
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#define EXCCAUSE_LEVEL1_INTERRUPT 4
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#define EXCCAUSE_ALLOCA 5
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#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6
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#define EXCCAUSE_SPECULATION 7
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#define EXCCAUSE_PRIVILEGED 8
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#define EXCCAUSE_UNALIGNED 9
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#define EXCCAUSE_ITLB_MISS 16
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#define EXCCAUSE_ITLB_MULTIHIT 17
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#define EXCCAUSE_ITLB_PRIVILEGE 18
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#define EXCCAUSE_ITLB_SIZE_RESTRICTION 19
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#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20
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#define EXCCAUSE_DTLB_MISS 24
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#define EXCCAUSE_DTLB_MULTIHIT 25
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#define EXCCAUSE_DTLB_PRIVILEGE 26
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#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
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#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
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#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
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#define EXCCAUSE_COPROCESSOR0_DISABLED 32
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#define EXCCAUSE_COPROCESSOR1_DISABLED 33
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#define EXCCAUSE_COPROCESSOR2_DISABLED 34
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#define EXCCAUSE_COPROCESSOR3_DISABLED 35
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#define EXCCAUSE_COPROCESSOR4_DISABLED 36
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#define EXCCAUSE_COPROCESSOR5_DISABLED 37
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#define EXCCAUSE_COPROCESSOR6_DISABLED 38
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#define EXCCAUSE_COPROCESSOR7_DISABLED 39
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/* PS register fields. */
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#define PS_WOE_BIT 18
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#define PS_CALLINC_SHIFT 16
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#define PS_CALLINC_MASK 0x00030000
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#define PS_OWB_SHIFT 8
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#define PS_OWB_MASK 0x00000F00
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#define PS_RING_SHIFT 6
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#define PS_RING_MASK 0x000000C0
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#define PS_UM_BIT 5
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#define PS_EXCM_BIT 4
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#define PS_INTLEVEL_SHIFT 0
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#define PS_INTLEVEL_MASK 0x0000000F
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/* DBREAKCn register fields. */
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#define DBREAKC_MASK_BIT 0
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#define DBREAKC_MASK_MASK 0x0000003F
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#define DBREAKC_LOAD_BIT 30
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#define DBREAKC_LOAD_MASK 0x40000000
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#define DBREAKC_STOR_BIT 31
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#define DBREAKC_STOR_MASK 0x80000000
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/* DEBUGCAUSE register fields. */
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#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
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#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
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#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
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#define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */
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#define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */
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#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
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#endif /* _XTENSA_SPECREG_H */
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