c927d74ec0
Add the Device Tree binding documentation for the Microsemi Ocelot interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
22 lines
740 B
Text
22 lines
740 B
Text
Microsemi Ocelot SoC ICPU Interrupt Controller
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Required properties:
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- compatible : should be "mscc,ocelot-icpu-intr"
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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- interrupt-parent : phandle of the CPU interrupt controller.
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- interrupts : Specifies the CPU interrupt the controller is connected to.
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Example:
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intc: interrupt-controller@70000070 {
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compatible = "mscc,ocelot-icpu-intr";
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reg = <0x70000070 0x70>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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