Suzuki K Poulose ebab6a7db2 coresight tmc etr: Setup AXI cache encoding for read transfers ... If the ETR supports split cache encoding (i.e, separate bits for read and write transfers) unlike the older version (where read and write transfers use the same encoding in AXICTL[2-5]). This feature is not advertised and has to be described by the static mask associated with the device id. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-08-28 16:05:49 +02:00
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coresight	coresight tmc etr: Setup AXI cache encoding for read transfers	2017-08-28 16:05:49 +02:00
intel_th	hwtracing: intel_th: use dev_groups and not dev_attrs for bus_type	2017-06-09 11:00:46 +02:00
stm	This release has a few updates:	2016-12-15 13:49:34 -08:00