c5b736d093
This is a significant rework of the low-level clock, PLL and Power Sleep Controller (PSC) implementation for the DaVinci family. The primary goal is to have better modeling if the hardware clocks and features with the aim of DVFS functionality. Highlights: - model PLLs and all PLL-derived clocks - model parent/child relationships of PLLs and clocks - convert to new clkdev layer - view clock frequency and refcount via /proc/davinci_clocks Special thanks to significant contributions and testing by David Brownell. Cc: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
35 lines
862 B
Text
35 lines
862 B
Text
if ARCH_DAVINCI
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menu "TI DaVinci Implementations"
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comment "DaVinci Core Type"
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config ARCH_DAVINCI644x
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default y
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bool "DaVinci 644x based system"
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comment "DaVinci Board Type"
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config MACH_DAVINCI_EVM
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bool "TI DaVinci EVM"
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default y
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depends on ARCH_DAVINCI644x
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help
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Configure this option to specify the whether the board used
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for development is a DaVinci EVM
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config DAVINCI_RESET_CLOCKS
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bool "Reset unused clocks during boot"
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depends on ARCH_DAVINCI
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help
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Say Y if you want to reset unused clocks during boot.
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This option saves power, but assumes all drivers are
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using the clock framework. Broken drivers that do not
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yet use clock framework may not work with this option.
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If you are booting from another operating system, you
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probably do not want this option enabled until your
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device drivers work properly.
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endmenu
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endif
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