pkgsrc-wip/verilog08/distinfo

$NetBSD: distinfo,v 1.1 2014/08/20 11:37:00 makoto Exp $

SHA1 (verilog-0.8.7.tar.gz) = 814f12a99463a637cb13e0d86755f762c5d90270
RMD160 (verilog-0.8.7.tar.gz) = 63fb4f9e1e85157010d480e5d66513d6c9ac4326
Size (verilog-0.8.7.tar.gz) = 1273972 bytes
SHA1 (patch-ad) = 909463388ea6bfd5b63a291cfa791da6f8c8f215
SHA1 (patch-cadpli_Makefile_in) = 938f0d1eb2d9665814be538b2f392eb1eaf02aef
SHA1 (patch-driver-vpi_Makefile_in) = 30bc59721b276c207e8ffbf38413ac04d6d3b1ac
SHA1 (patch-driver_Makefile_in) = b6a16b7aa5f7c31ee002a7bf2f54291eccce6ccf
SHA1 (patch-elab__net_cc) = 2ce14f39997ad5cf49a668c7ff386dba1c40261d
SHA1 (patch-ivlpp_Makefile_in) = 68b8849de075511a41c2cab7d8dac1938fb015df
SHA1 (patch-libveriuser_Makefile_in) = 39579b6b61797a5f2a491e8562a846d9e31553c3
SHA1 (patch-tgt-edif_Makefile_in) = 0de6b5af64fb79c92fc7e9546aa5f9f1f1c9ce79
SHA1 (patch-tgt-fpga_Makefile_in) = c58175877a597d9e5d8aa4ee7c83c1c8689a6988
SHA1 (patch-tgt-null_Makefile_in) = 689e3c94ebf6e31854fcbefe0f1d9046f92c2576
SHA1 (patch-tgt-pal_Makefile_in) = 937630191b18a6f6f2bbbaa5f8c25b3848b69dbd
SHA1 (patch-tgt-stub_Makefile_in) = 9cd13ce6a2bfe3379d20655e732f33b1203eb23c
SHA1 (patch-tgt-verilog_Makefile_in) = 7e7cdb85870f0ee82a6ad538225fb12d987624e0
SHA1 (patch-vpi_Makefile_in) = 439171cbcb60b8254c911b79b114543279314e52
SHA1 (patch-vvp_Makefile_in) = 3c22fb08eec4ef8a9df7ce60391c2f0a1e57ff41
Import verilog08-0.8.7 as wip/verilog08. Verilog 0.8 revived. Newer version said dropped the synthesis capability. (This version was picked up 2009-03 of cad/verilog and added user-destdir patches) Verilog-0.8 series has synthesize capability to xnf (Xilinx) and fpga(EDIF). Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in. 2014-08-20 13:37:00 +02:00			$NetBSD: distinfo,v 1.1 2014/08/20 11:37:00 makoto Exp $

			`SHA1 (verilog-0.8.7.tar.gz) = 814f12a99463a637cb13e0d86755f762c5d90270`
			`RMD160 (verilog-0.8.7.tar.gz) = 63fb4f9e1e85157010d480e5d66513d6c9ac4326`
			`Size (verilog-0.8.7.tar.gz) = 1273972 bytes`
			`SHA1 (patch-ad) = 909463388ea6bfd5b63a291cfa791da6f8c8f215`
			`SHA1 (patch-cadpli_Makefile_in) = 938f0d1eb2d9665814be538b2f392eb1eaf02aef`
			`SHA1 (patch-driver-vpi_Makefile_in) = 30bc59721b276c207e8ffbf38413ac04d6d3b1ac`
			`SHA1 (patch-driver_Makefile_in) = b6a16b7aa5f7c31ee002a7bf2f54291eccce6ccf`
			`SHA1 (patch-elab__net_cc) = 2ce14f39997ad5cf49a668c7ff386dba1c40261d`
			`SHA1 (patch-ivlpp_Makefile_in) = 68b8849de075511a41c2cab7d8dac1938fb015df`
			`SHA1 (patch-libveriuser_Makefile_in) = 39579b6b61797a5f2a491e8562a846d9e31553c3`
			`SHA1 (patch-tgt-edif_Makefile_in) = 0de6b5af64fb79c92fc7e9546aa5f9f1f1c9ce79`
			`SHA1 (patch-tgt-fpga_Makefile_in) = c58175877a597d9e5d8aa4ee7c83c1c8689a6988`
			`SHA1 (patch-tgt-null_Makefile_in) = 689e3c94ebf6e31854fcbefe0f1d9046f92c2576`
			`SHA1 (patch-tgt-pal_Makefile_in) = 937630191b18a6f6f2bbbaa5f8c25b3848b69dbd`
			`SHA1 (patch-tgt-stub_Makefile_in) = 9cd13ce6a2bfe3379d20655e732f33b1203eb23c`
			`SHA1 (patch-tgt-verilog_Makefile_in) = 7e7cdb85870f0ee82a6ad538225fb12d987624e0`
			`SHA1 (patch-vpi_Makefile_in) = 439171cbcb60b8254c911b79b114543279314e52`
			`SHA1 (patch-vvp_Makefile_in) = 3c22fb08eec4ef8a9df7ce60391c2f0a1e57ff41`