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Update HOMEPAGE.

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Makoto Fujiwara 2014-02-15 13:40:19 +00:00 committed by Thomas Klausner
parent 1f95d91b3b
commit 0b9dabdc28
1 changed files with 2 additions and 2 deletions
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verilog-current/Makefile
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@ -1,4 +1,4 @@
# $NetBSD: Makefile,v 1.3 2013/12/20 15:27:35 makoto Exp $ # $NetBSD: Makefile,v 1.4 2014/02/15 13:40:19 makoto Exp $
DISTNAME= verilog-${SNAPDATE} DISTNAME= verilog-${SNAPDATE}
PKGNAME= verilog-current-${SNAPDATE} PKGNAME= verilog-current-${SNAPDATE}
@ -6,7 +6,7 @@ CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
MAINTAINER= dmcmahill@NetBSD.org MAINTAINER= dmcmahill@NetBSD.org
HOMEPAGE= http://icarus.com/eda/verilog/index.html HOMEPAGE= http://iverilog.icarus.com/
COMMENT= Verilog simulation and synthesis tool (development snapshot version) COMMENT= Verilog simulation and synthesis tool (development snapshot version)
LICENSE= gnu-gpl-v2 LICENSE= gnu-gpl-v2