0669363a6a
Verilog 0.8 revived. Newer version said dropped the synthesis capability. (This version was picked up 2009-03 of cad/verilog and added user-destdir patches) Verilog-0.8 series has synthesize capability to xnf (Xilinx) and fpga(EDIF). Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.
34 lines
828 B
Text
34 lines
828 B
Text
@comment $NetBSD: PLIST,v 1.1 2014/08/20 11:37:00 makoto Exp $
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bin/iverilog-0.8
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bin/iverilog-vpi-0.8
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bin/vvp-0.8
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include/iverilog-0.8/_pli_types.h
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include/iverilog-0.8/acc_user.h
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include/iverilog-0.8/ivl_target.h
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include/iverilog-0.8/veriuser.h
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include/iverilog-0.8/vpi_user.h
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lib/ivl-0.8/cadpli.vpl
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lib/ivl-0.8/edif-s.conf
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lib/ivl-0.8/edif.conf
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lib/ivl-0.8/edif.tgt
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lib/ivl-0.8/fpga-s.conf
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lib/ivl-0.8/fpga.conf
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lib/ivl-0.8/fpga.tgt
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lib/ivl-0.8/ivl
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lib/ivl-0.8/ivlpp
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lib/ivl-0.8/null-s.conf
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lib/ivl-0.8/null.conf
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lib/ivl-0.8/null.tgt
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lib/ivl-0.8/system.sft
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lib/ivl-0.8/system.vpi
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lib/ivl-0.8/vvp-s.conf
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lib/ivl-0.8/vvp.conf
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lib/ivl-0.8/vvp.tgt
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lib/ivl-0.8/xnf-s.conf
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lib/ivl-0.8/xnf.conf
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lib/libveriuser-0.8.a
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lib/libvpi-0.8.a
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man/man1/iverilog-fpga-0.8.1
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man/man1/iverilog-vpi-0.8.1
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man/man1/iverilog-0.8.1
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man/man1/vvp-0.8.1
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