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pkgsrc/cad/covered/Makefile

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Recursive revision bump / recommended bump for gettext ABI change.
2006-02-06 00:08:03 +01:00
# $NetBSD: Makefile,v 1.10 2006/02/05 23:08:20 joerg Exp $
import covered-0.2.1 Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
2003-08-24 20:38:06 +02:00
#
update to covered-0.3 Changes since the last stable release: - User-specified FSM code coverage. By using command-line options or inline code specified by the user, FSM code coverage can be extracted from the design. This does not include the ability to automatically extract FSMs from the design (an ability that will be added in future stable releases). - Enhanced performance of the score command. A 3x - 5x speedup in the running time of the score command on the design should be expected with this release over past stable releases. - Enhanced readability of coverage reports. The coverage report look has been overhauled to produce a much more readable/understandable coverage report. - Several bug-fixes have been made, including coverage number calculation bugs. - Development and user documentation updates. - Enhanced regression suite.
2004-11-27 16:04:02 +01:00
DISTNAME= covered-0.3
Recursive revision bump / recommended bump for gettext ABI change.
2006-02-06 00:08:03 +01:00
PKGREVISION= 1
import covered-0.2.1 Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
2003-08-24 20:38:06 +02:00
CATEGORIES= cad
MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=covered/}
MAINTAINER= dmcmahill@NetBSD.org
HOMEPAGE= http://covered.sourceforge.net/
COMMENT= Verilog code coverage analyzer (stable release version)
bl3ify
2004-03-12 23:37:12 +01:00
PKG_INSTALLATION_TYPES= overwrite pkgviews
import covered-0.2.1 Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
2003-08-24 20:38:06 +02:00
BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison
DEPENDS+= verilog{,-current}-[0-9]*:../../cad/verilog
CONFLICTS+= covered-current-[0-9]*
Fix REPLACE_PERL: pathnames listed should be relative to ${WRKSRC}.
2003-09-02 01:34:57 +02:00
REPLACE_PERL= diags/verilog/check_test
import covered-0.2.1 Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
2003-08-24 20:38:06 +02:00
GNU_CONFIGURE= YES
Get rid of USE_PERL5. The new way to express needing the Perl executable around at either build-time or at run-time is: USE_TOOLS+= perl # build-time USE_TOOLS+= perl:run # run-time Also remove some places where perl5/buildlink3.mk was being included by a package Makefile, but all that the package wanted was the Perl executable.
2005-07-16 03:19:06 +02:00
USE_TOOLS+= gmake perl:run
import covered-0.2.1 Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
2003-08-24 20:38:06 +02:00
TEST_DIRS= ${WRKSRC}/diags/regress
Update to covered-0.2.2. From the NEWS file: This release is basically a 0.2.1 release with the available bug fixes patches applied to it. This should make getting a stable release less tedious.
2003-12-09 02:20:36 +01:00
TEST_TARGET= iverilog
import covered-0.2.1 Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
2003-08-24 20:38:06 +02:00
post-patch:
${CHMOD} 755 ${WRKSRC}/missing
bl3ify
2004-03-12 23:37:12 +01:00
pre-install:
${INSTALL_PROGRAM_DIR} ${PREFIX}/bin
${INSTALL_MAN_DIR} ${PREFIX}/man/man1
update to covered-0.3 Changes since the last stable release: - User-specified FSM code coverage. By using command-line options or inline code specified by the user, FSM code coverage can be extracted from the design. This does not include the ability to automatically extract FSMs from the design (an ability that will be added in future stable releases). - Enhanced performance of the score command. A 3x - 5x speedup in the running time of the score command on the design should be expected with this release over past stable releases. - Enhanced readability of coverage reports. The coverage report look has been overhauled to produce a much more readable/understandable coverage report. - Several bug-fixes have been made, including coverage number calculation bugs. - Development and user documentation updates. - Enhanced regression suite.
2004-11-27 16:04:02 +01:00
.include "../../devel/gperf/buildlink3.mk"
import covered-0.2.1 Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
2003-08-24 20:38:06 +02:00
.include "../../mk/bsd.pkg.mk"
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