Update cad/MyHDL from 0.9.0 to 0.10
pkgsrc packages altered:
- cad/MyHDL-gplcver
- cad/MyHDL-iverilog
- cad/py-MyHDL
upstream changelog
------------------------
What’s new in MyHDL 0.10
The block decorator
Rationale
The historical approach for hierarchy extraction in MyHDL suffers from
significant issues. This results in complex code, a number of non-intuitive API
concepts, and difficulties for future development.
In this release, a new block decorator is introduced to address these issues.
For an in-depth discussion, see mep-114.
API
block() :noindex:
The block decorator enables a method-based API which is more consistent,
simplifies implementation, and reduces the size of the myhdl namespace.
The methods work on block instances, created by calling a function
decorated with the block decorator:
@block
def myblock(<ports>):
...
return <instances>
inst = myblock(<port-associations>)
# inst supports the methods of the block instance API
The API on a block instance looks as follows:
<block_instance>.run_sim(duration=None)
Run a simulation “forever” (default) or for a specified duration.
<block_instance>.config_sim(backend='myhdl', trace=False)
- Optional simulation configuration:
- backend: Defaults to ‘myhdl
- trace: Enable waveform tracing, default False.
<block_instance>.quit_sim()
Quit an active simulation. This is method is currently required because
only a single simulation can be active.
<block_instance>.convert(hdl='Verilog', **kwargs)
- Converts MyHDL code to a target HDL.
- hdl: ‘VHDL’ or ‘Verilog’. Defaults to Verilog.
- Supported keyword arguments:
- path: Destination folder. Defaults to current working dir.
- name: Module and output file name. Defaults to self.mod.__name__.
- trace: Whether the testbench should dump all signal waveforms. Defaults to
False.
- testbench: Verilog only. Specifies whether a testbench should be created.
Defaults to True.
- timescale: timescale parameter. Defaults to ‘1ns/10ps’. Verilog only.
<block_instance>.verify_convert()
Verify conversion output, by comparing target HDL simulation log with MyHDL
simulation log.
<block_instance>.analyze_convert()
Analyze conversion output by compilation with target HDL compiler.
Backwards compatibility issues
In the 0.10 release, the old API still available next to the new API based on
the block decorator.
It is likely that the old API will be deprecated in a future release, resulting
in backwards incompatibility for legacy code. Therefore, users are encouraged
to start using the new API in their development methodology.
2018-04-12 17:08:58 +02:00
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# $NetBSD: Makefile.common,v 1.2 2018/04/12 15:08:58 mef Exp $
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Update MyHDL from 0.8.1 to 0.9.0
pkgsrc packages altered:
- cad/MyHDL-gplcver
- cad/MyHDL-iverilog
- cad/py-MyHDL
pkgsrc changes:
- Add common Makefile.common for MyHDL packages
- 0.9.0 supports now Python 3.x
- update LICENSE to gnu-lgpl-v2.1
- replace local patch in MyHDL-gplcver and use MAKE_FLAGS to enforce INCS
- set CC in MyHDL-gplcver
- setup test target in cad/py-MyHDL
- share common distinfo
- replace AUTO_MKDIRS with INSTALLATION_DIRS
- switch MASTER_SITES to GitHub
upstream changelog
==================
What’s new in MyHDL 0.9
Python 3 support
Experimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase.
See Python 3 Support for more info.
Interfaces (Conversion of attribute accesses)
Rationale
Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an interface: an object that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors.
The following is an example of an interface definition:
class Complex:
def __init__(self, min=-2, max=2):
self.real = Signal(intbv(0, min=min, max=max))
self.imag = Signal(intbv(0, min=min, max=max))
Although previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces.
The following is an example using the above Complex interface definition:
a,b = Complex(-8,8), Complex(-8,8)
c = Complex(-128,128)
def complex_multiply(clock, reset, a, b, c):
@always_seq(clock.posedge, reset=reset)
def cmult():
c.real.next = (a.real*b.real) - (a.imag*b.imag)
c.imag.next = (a.real*b.imag) + (a.imag*b.real)
return cmult
Solution
The proposed solution is to create unique names for attributes which are used by MyHDL generators. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the ”.” with an “_” for each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling.
Note that the MyHDL convertor supports interfaces, even though the target HDLs do not. This is another great example where the convertor supports a high-level feature that is not available in the target HDLs.
See also
For additional information see the original proposal mep-107.
Other noteworthy improvements
ConcatSignal interface
The interface of ConcatSignal was enhanced. In addition to signals, you can now also use constant values in the concatenation.
std_logic type ports
toVHDL() has a new attibute std_logic_ports. When set, only std_logic type ports are used in the interface of the top-level VHDL module.
Development flow
The MyHDL development flow has been modernized by moving to git and github for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration.
Acknowledgments
The Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic.
MyHDL development is a collaborative effort, as can be seen on github. Thanks to all who contributed with suggestions, issues and pull requests.
2016-10-09 05:15:57 +02:00
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#
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# used by cad/MyHDL-gplcver/Makefile
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# used by cad/MyHDL-iverilog/Makefile
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GITHUB_PROJECT= myhdl
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Update cad/MyHDL from 0.9.0 to 0.10
pkgsrc packages altered:
- cad/MyHDL-gplcver
- cad/MyHDL-iverilog
- cad/py-MyHDL
upstream changelog
------------------------
What’s new in MyHDL 0.10
The block decorator
Rationale
The historical approach for hierarchy extraction in MyHDL suffers from
significant issues. This results in complex code, a number of non-intuitive API
concepts, and difficulties for future development.
In this release, a new block decorator is introduced to address these issues.
For an in-depth discussion, see mep-114.
API
block() :noindex:
The block decorator enables a method-based API which is more consistent,
simplifies implementation, and reduces the size of the myhdl namespace.
The methods work on block instances, created by calling a function
decorated with the block decorator:
@block
def myblock(<ports>):
...
return <instances>
inst = myblock(<port-associations>)
# inst supports the methods of the block instance API
The API on a block instance looks as follows:
<block_instance>.run_sim(duration=None)
Run a simulation “forever” (default) or for a specified duration.
<block_instance>.config_sim(backend='myhdl', trace=False)
- Optional simulation configuration:
- backend: Defaults to ‘myhdl
- trace: Enable waveform tracing, default False.
<block_instance>.quit_sim()
Quit an active simulation. This is method is currently required because
only a single simulation can be active.
<block_instance>.convert(hdl='Verilog', **kwargs)
- Converts MyHDL code to a target HDL.
- hdl: ‘VHDL’ or ‘Verilog’. Defaults to Verilog.
- Supported keyword arguments:
- path: Destination folder. Defaults to current working dir.
- name: Module and output file name. Defaults to self.mod.__name__.
- trace: Whether the testbench should dump all signal waveforms. Defaults to
False.
- testbench: Verilog only. Specifies whether a testbench should be created.
Defaults to True.
- timescale: timescale parameter. Defaults to ‘1ns/10ps’. Verilog only.
<block_instance>.verify_convert()
Verify conversion output, by comparing target HDL simulation log with MyHDL
simulation log.
<block_instance>.analyze_convert()
Analyze conversion output by compilation with target HDL compiler.
Backwards compatibility issues
In the 0.10 release, the old API still available next to the new API based on
the block decorator.
It is likely that the old API will be deprecated in a future release, resulting
in backwards incompatibility for legacy code. Therefore, users are encouraged
to start using the new API in their development methodology.
2018-04-12 17:08:58 +02:00
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DISTNAME= myhdl-0.10
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Update MyHDL from 0.8.1 to 0.9.0
pkgsrc packages altered:
- cad/MyHDL-gplcver
- cad/MyHDL-iverilog
- cad/py-MyHDL
pkgsrc changes:
- Add common Makefile.common for MyHDL packages
- 0.9.0 supports now Python 3.x
- update LICENSE to gnu-lgpl-v2.1
- replace local patch in MyHDL-gplcver and use MAKE_FLAGS to enforce INCS
- set CC in MyHDL-gplcver
- setup test target in cad/py-MyHDL
- share common distinfo
- replace AUTO_MKDIRS with INSTALLATION_DIRS
- switch MASTER_SITES to GitHub
upstream changelog
==================
What’s new in MyHDL 0.9
Python 3 support
Experimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase.
See Python 3 Support for more info.
Interfaces (Conversion of attribute accesses)
Rationale
Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an interface: an object that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors.
The following is an example of an interface definition:
class Complex:
def __init__(self, min=-2, max=2):
self.real = Signal(intbv(0, min=min, max=max))
self.imag = Signal(intbv(0, min=min, max=max))
Although previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces.
The following is an example using the above Complex interface definition:
a,b = Complex(-8,8), Complex(-8,8)
c = Complex(-128,128)
def complex_multiply(clock, reset, a, b, c):
@always_seq(clock.posedge, reset=reset)
def cmult():
c.real.next = (a.real*b.real) - (a.imag*b.imag)
c.imag.next = (a.real*b.imag) + (a.imag*b.real)
return cmult
Solution
The proposed solution is to create unique names for attributes which are used by MyHDL generators. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the ”.” with an “_” for each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling.
Note that the MyHDL convertor supports interfaces, even though the target HDLs do not. This is another great example where the convertor supports a high-level feature that is not available in the target HDLs.
See also
For additional information see the original proposal mep-107.
Other noteworthy improvements
ConcatSignal interface
The interface of ConcatSignal was enhanced. In addition to signals, you can now also use constant values in the concatenation.
std_logic type ports
toVHDL() has a new attibute std_logic_ports. When set, only std_logic type ports are used in the interface of the top-level VHDL module.
Development flow
The MyHDL development flow has been modernized by moving to git and github for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration.
Acknowledgments
The Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic.
MyHDL development is a collaborative effort, as can be seen on github. Thanks to all who contributed with suggestions, issues and pull requests.
2016-10-09 05:15:57 +02:00
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CATEGORIES= cad python
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MASTER_SITES= ${MASTER_SITE_GITHUB:=jandecaluwe/}
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HOMEPAGE= http://myhdl.org/
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LICENSE= gnu-lgpl-v2.1
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DISTINFO_FILE= ${.CURDIR}/../../cad/py-MyHDL/distinfo
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PATCHDIR= ${.CURDIR}/../../cad/py-MyHDL/patches
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