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PKGREVISION bump for anything using python without a PYPKGPREFIX. This is a semi-manual PKGREVISION bump.
2019-04-25 09:32:34 +02:00
# $NetBSD: Makefile,v 1.28 2019/04/25 07:32:53 maya Exp $
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
#
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
DISTNAME= simulavr-1.0.0
PKGREVISION bump for anything using python without a PYPKGPREFIX. This is a semi-manual PKGREVISION bump.
2019-04-25 09:32:34 +02:00
PKGREVISION= 5
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
CATEGORIES= emulators
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
MASTER_SITES= http://download.savannah.gnu.org/releases/simulavr/
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
Point MAINTAINER to pkgsrc-users@NetBSD.org in the case where no developer is officially maintaining the package. The rationale for changing this from "tech-pkg" to "pkgsrc-users" is that it implies that any user can try to maintain the package (by submitting patches to the mailing list). Since the folks most likely to care about the package are the folks that want to use it or are already using it, this would leverage the energy of users who aren't developers.
2006-03-04 22:28:51 +01:00
MAINTAINER= pkgsrc-users@NetBSD.org
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
HOMEPAGE= http://www.nongnu.org/simulavr/
COMMENT= Simulator for Atmel AVR microcontrollers
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
LICENSE= gnu-gpl-v2
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
Add build dependency on avr-binutils and avr-gcc to fix build as these tools are required. Also use the correct style to depend on any version of doxygen.
2005-03-20 13:07:42 +01:00
BUILD_DEPENDS+= doxygen-[0-9]*:../../devel/doxygen
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
BUILD_DEPENDS+= avr-libc-[0-9]*:../../cross/avr-libc
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
CONFIGURE_ARGS+= --disable-tests
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
CONFIGURE_ARGS+= --enable-python=python${PYVERSSUFFIX}
CONFIGURE_ARGS+= --with-bfd=${PREFIX}/avr
(pkgsrc) simulavr asks for libiberty.a. With avr-gcc 4.5.3 and avr-binutils-2.23.2, binutils is installing libiberty.a But with new binutils-2.24, it won't install libiberty. Instead, avr-gcc-4.8.3 will provied libiberty. Makefile (of simulavr) now has pointer to PATH of libiberty now as: CONFIGURE_ARGS+= --with-libiberty=${PREFIX}/lib/gcc/avr (Add patches) patch-src_systemclock_cpp (rename from patch-src_systemclock.cpp) patch-src_systemclock_h patch-src_traceval_cpp patch-src_traceval_h clang flags as resize unresolved reference, backport from git repository (as of 2013-09-15). patch-examples_atmel_key_StdDefs_c Status: Locally Added passing argument 1 of 'strlen' differ in signedness [-Wpointer-sign]
2014-08-29 06:40:06 +02:00
CONFIGURE_ARGS+= --with-libiberty=${PREFIX}/lib/gcc/avr
If TeX is installed it is used to build a PDF. Since we don't install the PDF, there's no point in building it, so disable TeX auto-detection.
2014-06-13 05:41:46 +02:00
CONFIGURE_ENV+= TEX=no
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
# Following line does not work yet (examples/python directory)
#CONFIGURE_ENV+= az_python_use=true
#MAKE_ENV+= az_python_use=true
Racy build.
2013-11-29 13:57:28 +01:00
MAKE_JOBS_SAFE= no
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
USE_TOOLS+= makeinfo gmake
USE_LIBTOOL= yes
USE_LANGUAGES+= c c++
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
USE_PKGLOCALEDIR= yes
GNU_CONFIGURE= yes
pkglint says, INFO_FILES should be set to YES or yes.
2006-09-10 04:52:26 +02:00
INFO_FILES= yes
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
# Interim fix
SUBST_CLASSES+= prefix
*: Move SUBST_STAGE from post-patch to pre-configure Performing substitutions during post-patch breaks tools such as mkpatches, making it very difficult to regenerate correct patches after making changes, and often leading to substituted string replacements being committed.
2018-07-04 15:40:07 +02:00
SUBST_STAGE.prefix= pre-configure
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
SUBST_MESSAGE.prefix= Fix include path finding Python.h
SUBST_FILES.prefix= src/Makefile.in
SUBST_VARS.prefix= PREFIX
# Following SUBST_CLASSES are from diff against git version (as of 2013-08-08)
# See also
# http://savannah.nongnu.org/bugs/?35737
SUBST_CLASSES+= compare2
*: Move SUBST_STAGE from post-patch to pre-configure Performing substitutions during post-patch breaks tools such as mkpatches, making it very difficult to regenerate correct patches after making changes, and often leading to substituted string replacements being committed.
2018-07-04 15:40:07 +02:00
SUBST_STAGE.compare2= pre-configure
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
SUBST_MESSAGE.compare2= Convert poisoned SIG_OUTPUT_COMPARE2 to TIMER2_COMP_vect
SUBST_FILES.compare2= examples/atmega128_timer/main.c
SUBST_FILES.compare2+= examples/python/example.c
SUBST_FILES.compare2+= examples/python/example_io.c
SUBST_FILES.compare2+= examples/python/ex_pinout.c
SUBST_FILES.compare2+= regress/timertest/timer_8bit_ctc.c
SUBST_SED.compare2= -e 's/SIG_OUTPUT_COMPARE2/TIMER2_COMP_vect/g'
# StdDefs.h:66:33: error: attempt to use poisoned "SIG_UART0_RECV"
# StdDefs.h:67:39: error: attempt to use poisoned "SIG_UART0_DATA"
# kb.c:39:8: error: attempt to use poisoned "SIG_INTERRUPT0"
SUBST_CLASSES+= uart0
*: Move SUBST_STAGE from post-patch to pre-configure Performing substitutions during post-patch breaks tools such as mkpatches, making it very difficult to regenerate correct patches after making changes, and often leading to substituted string replacements being committed.
2018-07-04 15:40:07 +02:00
SUBST_STAGE.uart0= pre-configure
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
SUBST_MESSAGE.uart0= Convert poisoned SIG_UART0_RECV to USART0_RX_vect
SUBST_FILES.uart0= examples/atmel_key/StdDefs.h
SUBST_SED.uart0= -e 's/SIG_UART0_RECV/USART0_RX_vect/g'
SUBST_SED.uart0+= -e 's/SIG_UART0_DATA/USART0_UDRE_vect/g'
SUBST_CLASSES+= intrpt0
*: Move SUBST_STAGE from post-patch to pre-configure Performing substitutions during post-patch breaks tools such as mkpatches, making it very difficult to regenerate correct patches after making changes, and often leading to substituted string replacements being committed.
2018-07-04 15:40:07 +02:00
SUBST_STAGE.intrpt0= pre-configure
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
SUBST_MESSAGE.intrpt0= Convert poisoned SIG_INTERRUPT0 to INT0_vect
SUBST_FILES.intrpt0= examples/atmel_key/kb.c
SUBST_FILES.intrpt0+= examples/python/multicore.c
SUBST_FILES.intrpt0+= regress/extinttest/ext_int0.c
SUBST_SED.intrpt0= -e 's/SIG_INTERRUPT0/INT0_vect/g'
# Following case, see patches
# regress/timertest/timer_16bit.c:ISR(SIG_OUTPUT_COMPARE3B) {
SUBST_CLASSES+= makeinfo
SUBST_STAGE.makeinfo= post-configure
SUBST_MESSAGE.makeinfo= set MAKEINFO path (to avoid work-directory references included)
SUBST_FILES.makeinfo= examples/anacomp/Makefile.in
SUBST_FILES.makeinfo+= examples/python/Makefile.in
SUBST_SED.makeinfo= -e 's,@MAKEINFO@,${PREFIX}/bin/makeinfo,g'
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
# gcc 2.95 gives warnings that it cannot inline all functions.
BUILDLINK_TRANSFORM+= rm:-Werror
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
.include "../../cross/avr-binutils/buildlink3.mk"
.include "../../cross/avr-gcc/buildlink3.mk"
.include "../../devel/swig/buildlink3.mk"
Add missing mk/curses buildlink. Bump PKGREVISION
2011-12-17 11:15:28 +01:00
.include "../../mk/curses.buildlink3.mk"
(pkgsrc) Raw simulavr-1.0.0 does not build. Some patches, and SUBST to convert MACROS etc., are added reflecting git repository (These will be unnecessary at next release, hopefully). (Upstream) Bump the version simulavr-0.1.2.1 to simulavr-1.0.0 (From manual-1.0.pdf) What features are new: - Run multiple AVR devices in one simulation. (only with interpreter interfaces or special application linked against simulavr library) Multiple cores can run where each has a different clock frequency. - Connect multiple AVR core pins to other devices like LCD, LED and others. (environment) - Connect multiple AVR cores to multiple avr-gdb instances. (each on its own socket/port number, but see first point for running multiple avr cores) - Write simulation scripts in Tcl/Tk or Python, other languages could be added by simply adding swig scripts! - Tracing the execution of the program, these traces support all debugging information directly from the ELF-file. - The traces run step by step for each device so you see all actions in the multiple devices in time-correct order. - Every interrupt call is visible. - Interrupt statistics with latency, longest and shortest execution time and some more. - There is a simple text based UI interface to add LCD, switches, LEDs or other components and can modify it during simulation, so there is no longer a need to enter a pin value during execution. (Tcl/Tk based) - Execution timing should be nearly accurate, different access times for internal RAM / external RAM / EEPROM and other hardware components are simulated. - A pseudo core hardware component is introduced to do "printf" debugging. This "device" is connected to a normal named UNIX socket so you do not have to waste a UART or other hardware in your test environment. (How?) - ELF-file loading is supported, no objcopy needed anymore. - Execution speed is tuned a lot, most hardware simulations are now only done if needed. - External IO pins which are not ports are also available. (E.g. ADC7 and ADC8 on ATmega8 in TQFP package.) - External I/O and some internal states of hardware units (link prescaler counter and interrupt states) can be dumped ot into a VCD trace to analyse I/O behaviour and timing. Or you can use it for tests.
2013-09-12 08:20:35 +02:00
.include "../../lang/python/pyversion.mk"
.include "../../lang/${PYPACKAGE}/buildlink3.mk"
.include "../../lang/tcl/buildlink3.mk"
Initial import of simulavr, contributed by Ola Eriksson in PR pkg/27596. The Simulavr program is a simulator for the Atmel AVR family of microcontrollers. Simulavr can be used either standalone or as a remote target for gdb. When used in gdbserver mode, the simulator is used as a backend so that gdb can be used as a source level debugger for AVR programs.
2004-12-30 20:49:08 +01:00
.include "../../mk/bsd.pkg.mk"
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