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2019-06-02 11:48:29 +02:00
@comment $NetBSD: PLIST,v 1.12 2019/06/02 09:48:29 adam Exp $
bin/FileCheck
bin/bugpoint
bin/count
bin/dsymutil
bin/llc
bin/lli
bin/lli-child-target
bin/llvm-PerfectShuffle
bin/llvm-ar
bin/llvm-as
bin/llvm-bcanalyzer
bin/llvm-c-test
bin/llvm-cat
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
bin/llvm-cfi-verify
bin/llvm-config
bin/llvm-cov
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
bin/llvm-cvtres
bin/llvm-cxxdump
bin/llvm-cxxfilt
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
bin/llvm-cxxmap
bin/llvm-diff
bin/llvm-dis
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
bin/llvm-dlltool
bin/llvm-dwarfdump
bin/llvm-dwp
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
bin/llvm-elfabi
bin/llvm-exegesis
bin/llvm-extract
bin/llvm-lib
bin/llvm-link
bin/llvm-lto
bin/llvm-lto2
bin/llvm-mc
bin/llvm-mca
bin/llvm-modextract
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
bin/llvm-mt
bin/llvm-nm
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
bin/llvm-objcopy
bin/llvm-objdump
bin/llvm-opt-report
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
bin/llvm-pdbutil
bin/llvm-profdata
bin/llvm-ranlib
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
bin/llvm-rc
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
bin/llvm-readelf
bin/llvm-readobj
bin/llvm-rtdyld
bin/llvm-size
bin/llvm-split
bin/llvm-stress
bin/llvm-strings
bin/llvm-strip
bin/llvm-symbolizer
bin/llvm-tblgen
bin/llvm-undname
bin/llvm-xray
bin/not
bin/obj2yaml
bin/opt
bin/sancov
bin/sanstats
bin/verify-uselistorder
bin/yaml-bench
bin/yaml2obj
include/llvm-c/Analysis.h
include/llvm-c/BitReader.h
include/llvm-c/BitWriter.h
include/llvm-c/Comdat.h
include/llvm-c/Core.h
include/llvm-c/DataTypes.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm-c/DebugInfo.h
include/llvm-c/Disassembler.h
include/llvm-c/DisassemblerTypes.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm-c/Error.h
include/llvm-c/ErrorHandling.h
include/llvm-c/ExecutionEngine.h
include/llvm-c/IRReader.h
include/llvm-c/Initialization.h
include/llvm-c/LinkTimeOptimizer.h
include/llvm-c/Linker.h
include/llvm-c/Object.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm-c/OptRemarks.h
include/llvm-c/OrcBindings.h
include/llvm-c/Support.h
include/llvm-c/Target.h
include/llvm-c/TargetMachine.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm-c/Transforms/AggressiveInstCombine.h
include/llvm-c/Transforms/Coroutines.h
include/llvm-c/Transforms/IPO.h
include/llvm-c/Transforms/InstCombine.h
include/llvm-c/Transforms/PassManagerBuilder.h
include/llvm-c/Transforms/Scalar.h
include/llvm-c/Transforms/Utils.h
include/llvm-c/Transforms/Vectorize.h
include/llvm-c/Types.h
include/llvm-c/lto.h
include/llvm/ADT/APFloat.h
include/llvm/ADT/APInt.h
include/llvm/ADT/APSInt.h
include/llvm/ADT/AllocatorList.h
include/llvm/ADT/Any.h
include/llvm/ADT/ArrayRef.h
include/llvm/ADT/BitVector.h
include/llvm/ADT/BitmaskEnum.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/ADT/BreadthFirstIterator.h
include/llvm/ADT/CachedHashString.h
include/llvm/ADT/DAGDeltaAlgorithm.h
include/llvm/ADT/DeltaAlgorithm.h
include/llvm/ADT/DenseMap.h
include/llvm/ADT/DenseMapInfo.h
include/llvm/ADT/DenseSet.h
include/llvm/ADT/DepthFirstIterator.h
include/llvm/ADT/EpochTracker.h
include/llvm/ADT/EquivalenceClasses.h
include/llvm/ADT/FoldingSet.h
include/llvm/ADT/FunctionExtras.h
include/llvm/ADT/GraphTraits.h
include/llvm/ADT/Hashing.h
include/llvm/ADT/ImmutableList.h
include/llvm/ADT/ImmutableMap.h
include/llvm/ADT/ImmutableSet.h
include/llvm/ADT/IndexedMap.h
include/llvm/ADT/IntEqClasses.h
include/llvm/ADT/IntervalMap.h
include/llvm/ADT/IntrusiveRefCntPtr.h
include/llvm/ADT/MapVector.h
include/llvm/ADT/None.h
include/llvm/ADT/Optional.h
include/llvm/ADT/PackedVector.h
include/llvm/ADT/PointerEmbeddedInt.h
include/llvm/ADT/PointerIntPair.h
include/llvm/ADT/PointerSumType.h
include/llvm/ADT/PointerUnion.h
include/llvm/ADT/PostOrderIterator.h
include/llvm/ADT/PriorityQueue.h
include/llvm/ADT/PriorityWorklist.h
include/llvm/ADT/SCCIterator.h
include/llvm/ADT/STLExtras.h
include/llvm/ADT/ScopeExit.h
include/llvm/ADT/ScopedHashTable.h
include/llvm/ADT/Sequence.h
include/llvm/ADT/SetOperations.h
include/llvm/ADT/SetVector.h
include/llvm/ADT/SmallBitVector.h
include/llvm/ADT/SmallPtrSet.h
include/llvm/ADT/SmallSet.h
include/llvm/ADT/SmallString.h
include/llvm/ADT/SmallVector.h
include/llvm/ADT/SparseBitVector.h
include/llvm/ADT/SparseMultiSet.h
include/llvm/ADT/SparseSet.h
include/llvm/ADT/Statistic.h
include/llvm/ADT/StringExtras.h
include/llvm/ADT/StringMap.h
include/llvm/ADT/StringRef.h
include/llvm/ADT/StringSet.h
include/llvm/ADT/StringSwitch.h
include/llvm/ADT/TinyPtrVector.h
include/llvm/ADT/Triple.h
include/llvm/ADT/Twine.h
include/llvm/ADT/UniqueVector.h
include/llvm/ADT/VariadicFunction.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/ADT/bit.h
include/llvm/ADT/edit_distance.h
include/llvm/ADT/ilist.h
include/llvm/ADT/ilist_base.h
include/llvm/ADT/ilist_iterator.h
include/llvm/ADT/ilist_node.h
include/llvm/ADT/ilist_node_base.h
include/llvm/ADT/ilist_node_options.h
include/llvm/ADT/iterator.h
include/llvm/ADT/iterator_range.h
include/llvm/ADT/simple_ilist.h
include/llvm/Analysis/AliasAnalysis.h
include/llvm/Analysis/AliasAnalysisEvaluator.h
include/llvm/Analysis/AliasSetTracker.h
include/llvm/Analysis/AssumptionCache.h
include/llvm/Analysis/BasicAliasAnalysis.h
include/llvm/Analysis/BlockFrequencyInfo.h
include/llvm/Analysis/BlockFrequencyInfoImpl.h
include/llvm/Analysis/BranchProbabilityInfo.h
include/llvm/Analysis/CFG.h
include/llvm/Analysis/CFGPrinter.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Analysis/CFLAliasAnalysisUtils.h
include/llvm/Analysis/CFLAndersAliasAnalysis.h
include/llvm/Analysis/CFLSteensAliasAnalysis.h
include/llvm/Analysis/CGSCCPassManager.h
include/llvm/Analysis/CallGraph.h
include/llvm/Analysis/CallGraphSCCPass.h
include/llvm/Analysis/CallPrinter.h
include/llvm/Analysis/CaptureTracking.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Analysis/CmpInstAnalysis.h
include/llvm/Analysis/CodeMetrics.h
include/llvm/Analysis/ConstantFolding.h
include/llvm/Analysis/DOTGraphTraitsPass.h
include/llvm/Analysis/DemandedBits.h
include/llvm/Analysis/DependenceAnalysis.h
include/llvm/Analysis/DivergenceAnalysis.h
include/llvm/Analysis/DomPrinter.h
include/llvm/Analysis/DominanceFrontier.h
include/llvm/Analysis/DominanceFrontierImpl.h
include/llvm/Analysis/EHPersonalities.h
include/llvm/Analysis/GlobalsModRef.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Analysis/GuardUtils.h
include/llvm/Analysis/IVDescriptors.h
include/llvm/Analysis/IVUsers.h
include/llvm/Analysis/IndirectCallPromotionAnalysis.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Analysis/IndirectCallVisitor.h
include/llvm/Analysis/InlineCost.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Analysis/InstructionPrecedenceTracking.h
include/llvm/Analysis/InstructionSimplify.h
include/llvm/Analysis/Interval.h
include/llvm/Analysis/IntervalIterator.h
include/llvm/Analysis/IntervalPartition.h
include/llvm/Analysis/IteratedDominanceFrontier.h
include/llvm/Analysis/LazyBlockFrequencyInfo.h
include/llvm/Analysis/LazyBranchProbabilityInfo.h
include/llvm/Analysis/LazyCallGraph.h
include/llvm/Analysis/LazyValueInfo.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Analysis/LegacyDivergenceAnalysis.h
include/llvm/Analysis/Lint.h
include/llvm/Analysis/Loads.h
include/llvm/Analysis/LoopAccessAnalysis.h
include/llvm/Analysis/LoopAnalysisManager.h
include/llvm/Analysis/LoopInfo.h
include/llvm/Analysis/LoopInfoImpl.h
include/llvm/Analysis/LoopIterator.h
include/llvm/Analysis/LoopPass.h
include/llvm/Analysis/LoopUnrollAnalyzer.h
include/llvm/Analysis/MemoryBuiltins.h
include/llvm/Analysis/MemoryDependenceAnalysis.h
include/llvm/Analysis/MemoryLocation.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Analysis/MemorySSA.h
include/llvm/Analysis/MemorySSAUpdater.h
include/llvm/Analysis/ModuleSummaryAnalysis.h
include/llvm/Analysis/MustExecute.h
include/llvm/Analysis/ObjCARCAliasAnalysis.h
include/llvm/Analysis/ObjCARCAnalysisUtils.h
include/llvm/Analysis/ObjCARCInstKind.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Analysis/OptimizationRemarkEmitter.h
include/llvm/Analysis/OrderedBasicBlock.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Analysis/OrderedInstructions.h
include/llvm/Analysis/PHITransAddr.h
include/llvm/Analysis/Passes.h
include/llvm/Analysis/PhiValues.h
include/llvm/Analysis/PostDominators.h
include/llvm/Analysis/ProfileSummaryInfo.h
include/llvm/Analysis/PtrUseVisitor.h
include/llvm/Analysis/RegionInfo.h
include/llvm/Analysis/RegionInfoImpl.h
include/llvm/Analysis/RegionIterator.h
include/llvm/Analysis/RegionPass.h
include/llvm/Analysis/RegionPrinter.h
include/llvm/Analysis/ScalarEvolution.h
include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h
include/llvm/Analysis/ScalarEvolutionExpander.h
include/llvm/Analysis/ScalarEvolutionExpressions.h
include/llvm/Analysis/ScalarEvolutionNormalization.h
include/llvm/Analysis/ScopedNoAliasAA.h
include/llvm/Analysis/SparsePropagation.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Analysis/StackSafetyAnalysis.h
include/llvm/Analysis/SyncDependenceAnalysis.h
include/llvm/Analysis/SyntheticCountsUtils.h
include/llvm/Analysis/TargetFolder.h
include/llvm/Analysis/TargetLibraryInfo.def
include/llvm/Analysis/TargetLibraryInfo.h
include/llvm/Analysis/TargetTransformInfo.h
include/llvm/Analysis/TargetTransformInfoImpl.h
include/llvm/Analysis/Trace.h
include/llvm/Analysis/TypeBasedAliasAnalysis.h
include/llvm/Analysis/TypeMetadataUtils.h
include/llvm/Analysis/Utils/Local.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Analysis/ValueLattice.h
include/llvm/Analysis/ValueLatticeUtils.h
include/llvm/Analysis/ValueTracking.h
include/llvm/Analysis/VectorUtils.h
include/llvm/AsmParser/Parser.h
include/llvm/AsmParser/SlotMapping.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/BinaryFormat/AMDGPUMetadataVerifier.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/BinaryFormat/COFF.h
include/llvm/BinaryFormat/Dwarf.def
include/llvm/BinaryFormat/Dwarf.h
include/llvm/BinaryFormat/DynamicTags.def
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/BinaryFormat/ELF.h
include/llvm/BinaryFormat/ELFRelocs/AArch64.def
include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/BinaryFormat/ELFRelocs/ARC.def
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/BinaryFormat/ELFRelocs/ARM.def
include/llvm/BinaryFormat/ELFRelocs/AVR.def
include/llvm/BinaryFormat/ELFRelocs/BPF.def
include/llvm/BinaryFormat/ELFRelocs/Hexagon.def
include/llvm/BinaryFormat/ELFRelocs/Lanai.def
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/BinaryFormat/ELFRelocs/MSP430.def
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/BinaryFormat/ELFRelocs/Mips.def
include/llvm/BinaryFormat/ELFRelocs/PowerPC.def
include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def
include/llvm/BinaryFormat/ELFRelocs/RISCV.def
include/llvm/BinaryFormat/ELFRelocs/Sparc.def
include/llvm/BinaryFormat/ELFRelocs/SystemZ.def
include/llvm/BinaryFormat/ELFRelocs/i386.def
include/llvm/BinaryFormat/ELFRelocs/x86_64.def
include/llvm/BinaryFormat/MachO.def
include/llvm/BinaryFormat/MachO.h
include/llvm/BinaryFormat/Magic.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/BinaryFormat/MsgPack.def
include/llvm/BinaryFormat/MsgPack.h
include/llvm/BinaryFormat/MsgPackReader.h
include/llvm/BinaryFormat/MsgPackTypes.h
include/llvm/BinaryFormat/MsgPackWriter.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/BinaryFormat/Wasm.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/BinaryFormat/WasmRelocs.def
include/llvm/Bitcode/BitCodes.h
include/llvm/Bitcode/BitcodeReader.h
include/llvm/Bitcode/BitcodeWriter.h
include/llvm/Bitcode/BitcodeWriterPass.h
include/llvm/Bitcode/BitstreamReader.h
include/llvm/Bitcode/BitstreamWriter.h
include/llvm/Bitcode/LLVMBitCodes.h
include/llvm/CodeGen/AccelTable.h
include/llvm/CodeGen/Analysis.h
include/llvm/CodeGen/AsmPrinter.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/CodeGen/AsmPrinterHandler.h
include/llvm/CodeGen/AtomicExpandUtils.h
include/llvm/CodeGen/BasicTTIImpl.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/CodeGen/BuiltinGCs.h
include/llvm/CodeGen/CalcSpillWeights.h
include/llvm/CodeGen/CallingConvLower.h
include/llvm/CodeGen/CommandFlags.inc
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/CostTable.h
include/llvm/CodeGen/DAGCombine.h
include/llvm/CodeGen/DFAPacketizer.h
include/llvm/CodeGen/DIE.h
include/llvm/CodeGen/DIEValue.def
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/CodeGen/DbgEntityHistoryCalculator.h
include/llvm/CodeGen/DebugHandlerBase.h
include/llvm/CodeGen/DwarfStringPoolEntry.h
include/llvm/CodeGen/EdgeBundles.h
include/llvm/CodeGen/ExecutionDomainFix.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/ExpandReductions.h
include/llvm/CodeGen/FastISel.h
include/llvm/CodeGen/FaultMaps.h
include/llvm/CodeGen/FunctionLoweringInfo.h
include/llvm/CodeGen/GCMetadata.h
include/llvm/CodeGen/GCMetadataPrinter.h
include/llvm/CodeGen/GCStrategy.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/CodeGen/GlobalISel/CSEInfo.h
include/llvm/CodeGen/GlobalISel/CSEMIRBuilder.h
include/llvm/CodeGen/GlobalISel/CallLowering.h
include/llvm/CodeGen/GlobalISel/Combiner.h
include/llvm/CodeGen/GlobalISel/CombinerHelper.h
include/llvm/CodeGen/GlobalISel/CombinerInfo.h
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/GlobalISel/GISelWorkList.h
include/llvm/CodeGen/GlobalISel/IRTranslator.h
include/llvm/CodeGen/GlobalISel/InstructionSelect.h
include/llvm/CodeGen/GlobalISel/InstructionSelector.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
include/llvm/CodeGen/GlobalISel/Legalizer.h
include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/GlobalISel/Localizer.h
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
include/llvm/CodeGen/GlobalISel/RegBankSelect.h
include/llvm/CodeGen/GlobalISel/RegisterBank.h
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
include/llvm/CodeGen/GlobalISel/Types.h
include/llvm/CodeGen/GlobalISel/Utils.h
include/llvm/CodeGen/ISDOpcodes.h
include/llvm/CodeGen/IntrinsicLowering.h
include/llvm/CodeGen/LatencyPriorityQueue.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/LazyMachineBlockFrequencyInfo.h
include/llvm/CodeGen/LexicalScopes.h
include/llvm/CodeGen/LinkAllAsmWriterComponents.h
include/llvm/CodeGen/LinkAllCodegenComponents.h
include/llvm/CodeGen/LiveInterval.h
include/llvm/CodeGen/LiveIntervalUnion.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/LiveIntervals.h
include/llvm/CodeGen/LivePhysRegs.h
include/llvm/CodeGen/LiveRangeEdit.h
include/llvm/CodeGen/LiveRegMatrix.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/LiveRegUnits.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/LiveStacks.h
include/llvm/CodeGen/LiveVariables.h
include/llvm/CodeGen/LoopTraversal.h
include/llvm/CodeGen/LowLevelType.h
include/llvm/CodeGen/MIRParser/MIRParser.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/MIRPrinter.h
include/llvm/CodeGen/MIRYamlMapping.h
include/llvm/CodeGen/MachORelocation.h
include/llvm/CodeGen/MachineBasicBlock.h
include/llvm/CodeGen/MachineBlockFrequencyInfo.h
include/llvm/CodeGen/MachineBranchProbabilityInfo.h
include/llvm/CodeGen/MachineCombinerPattern.h
include/llvm/CodeGen/MachineConstantPool.h
include/llvm/CodeGen/MachineDominanceFrontier.h
include/llvm/CodeGen/MachineDominators.h
include/llvm/CodeGen/MachineFrameInfo.h
include/llvm/CodeGen/MachineFunction.h
include/llvm/CodeGen/MachineFunctionPass.h
include/llvm/CodeGen/MachineInstr.h
include/llvm/CodeGen/MachineInstrBuilder.h
include/llvm/CodeGen/MachineInstrBundle.h
include/llvm/CodeGen/MachineInstrBundleIterator.h
include/llvm/CodeGen/MachineJumpTableInfo.h
include/llvm/CodeGen/MachineLoopInfo.h
include/llvm/CodeGen/MachineMemOperand.h
include/llvm/CodeGen/MachineModuleInfo.h
include/llvm/CodeGen/MachineModuleInfoImpls.h
include/llvm/CodeGen/MachineOperand.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/MachineOptimizationRemarkEmitter.h
include/llvm/CodeGen/MachineOutliner.h
include/llvm/CodeGen/MachinePassRegistry.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/CodeGen/MachinePipeliner.h
include/llvm/CodeGen/MachinePostDominators.h
include/llvm/CodeGen/MachineRegionInfo.h
include/llvm/CodeGen/MachineRegisterInfo.h
include/llvm/CodeGen/MachineSSAUpdater.h
include/llvm/CodeGen/MachineScheduler.h
include/llvm/CodeGen/MachineTraceMetrics.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/MacroFusion.h
include/llvm/CodeGen/PBQP/CostAllocator.h
include/llvm/CodeGen/PBQP/Graph.h
include/llvm/CodeGen/PBQP/Math.h
include/llvm/CodeGen/PBQP/ReductionRules.h
include/llvm/CodeGen/PBQP/Solution.h
include/llvm/CodeGen/PBQPRAConstraint.h
include/llvm/CodeGen/ParallelCG.h
include/llvm/CodeGen/Passes.h
include/llvm/CodeGen/PreISelIntrinsicLowering.h
include/llvm/CodeGen/PseudoSourceValue.h
include/llvm/CodeGen/ReachingDefAnalysis.h
include/llvm/CodeGen/RegAllocPBQP.h
include/llvm/CodeGen/RegAllocRegistry.h
include/llvm/CodeGen/RegisterClassInfo.h
include/llvm/CodeGen/RegisterPressure.h
include/llvm/CodeGen/RegisterScavenging.h
include/llvm/CodeGen/RegisterUsageInfo.h
include/llvm/CodeGen/ResourcePriorityQueue.h
include/llvm/CodeGen/RuntimeLibcalls.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/SDNodeProperties.td
include/llvm/CodeGen/ScheduleDAG.h
include/llvm/CodeGen/ScheduleDAGInstrs.h
include/llvm/CodeGen/ScheduleDAGMutation.h
include/llvm/CodeGen/ScheduleDFS.h
include/llvm/CodeGen/ScheduleHazardRecognizer.h
include/llvm/CodeGen/SchedulerRegistry.h
include/llvm/CodeGen/ScoreboardHazardRecognizer.h
include/llvm/CodeGen/SelectionDAG.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
include/llvm/CodeGen/SelectionDAGISel.h
include/llvm/CodeGen/SelectionDAGNodes.h
include/llvm/CodeGen/SelectionDAGTargetInfo.h
include/llvm/CodeGen/SlotIndexes.h
include/llvm/CodeGen/StackMaps.h
include/llvm/CodeGen/StackProtector.h
include/llvm/CodeGen/TailDuplicator.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/TargetCallingConv.h
include/llvm/CodeGen/TargetFrameLowering.h
include/llvm/CodeGen/TargetInstrInfo.h
include/llvm/CodeGen/TargetLowering.h
include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/TargetOpcodes.h
include/llvm/CodeGen/TargetPassConfig.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/TargetRegisterInfo.h
include/llvm/CodeGen/TargetSchedule.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/CodeGen/TargetSubtargetInfo.h
include/llvm/CodeGen/UnreachableBlockElim.h
include/llvm/CodeGen/ValueTypes.h
include/llvm/CodeGen/ValueTypes.td
include/llvm/CodeGen/VirtRegMap.h
include/llvm/CodeGen/WasmEHFuncInfo.h
include/llvm/CodeGen/WinEHFuncInfo.h
include/llvm/Config/AsmParsers.def
include/llvm/Config/AsmPrinters.def
include/llvm/Config/Disassemblers.def
include/llvm/Config/Targets.def
include/llvm/Config/abi-breaking.h
include/llvm/Config/llvm-config.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/CodeView/AppendingTypeTableBuilder.h
include/llvm/DebugInfo/CodeView/CVRecord.h
include/llvm/DebugInfo/CodeView/CVSymbolVisitor.h
include/llvm/DebugInfo/CodeView/CVTypeVisitor.h
include/llvm/DebugInfo/CodeView/CodeView.h
include/llvm/DebugInfo/CodeView/CodeViewError.h
include/llvm/DebugInfo/CodeView/CodeViewRecordIO.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/CodeViewSymbols.def
include/llvm/DebugInfo/CodeView/CodeViewTypes.def
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/CodeView/ContinuationRecordBuilder.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/DebugChecksumsSubsection.h
include/llvm/DebugInfo/CodeView/DebugCrossExSubsection.h
include/llvm/DebugInfo/CodeView/DebugCrossImpSubsection.h
include/llvm/DebugInfo/CodeView/DebugFrameDataSubsection.h
include/llvm/DebugInfo/CodeView/DebugInlineeLinesSubsection.h
include/llvm/DebugInfo/CodeView/DebugLinesSubsection.h
include/llvm/DebugInfo/CodeView/DebugStringTableSubsection.h
include/llvm/DebugInfo/CodeView/DebugSubsection.h
include/llvm/DebugInfo/CodeView/DebugSubsectionRecord.h
include/llvm/DebugInfo/CodeView/DebugSubsectionVisitor.h
include/llvm/DebugInfo/CodeView/DebugSymbolRVASubsection.h
include/llvm/DebugInfo/CodeView/DebugSymbolsSubsection.h
include/llvm/DebugInfo/CodeView/DebugUnknownSubsection.h
include/llvm/DebugInfo/CodeView/EnumTables.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/Formatters.h
include/llvm/DebugInfo/CodeView/FunctionId.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/GUID.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/CodeView/GlobalTypeTableBuilder.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
include/llvm/DebugInfo/CodeView/Line.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/CodeView/MergingTypeTableBuilder.h
include/llvm/DebugInfo/CodeView/RecordName.h
include/llvm/DebugInfo/CodeView/RecordSerialization.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/CodeView/SimpleTypeSerializer.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/StringsAndChecksums.h
include/llvm/DebugInfo/CodeView/SymbolDeserializer.h
include/llvm/DebugInfo/CodeView/SymbolDumpDelegate.h
include/llvm/DebugInfo/CodeView/SymbolDumper.h
include/llvm/DebugInfo/CodeView/SymbolRecord.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/CodeView/SymbolRecordHelpers.h
include/llvm/DebugInfo/CodeView/SymbolRecordMapping.h
include/llvm/DebugInfo/CodeView/SymbolSerializer.h
include/llvm/DebugInfo/CodeView/SymbolVisitorCallbackPipeline.h
include/llvm/DebugInfo/CodeView/SymbolVisitorCallbacks.h
include/llvm/DebugInfo/CodeView/SymbolVisitorDelegate.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/TypeCollection.h
include/llvm/DebugInfo/CodeView/TypeDeserializer.h
include/llvm/DebugInfo/CodeView/TypeDumpVisitor.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/CodeView/TypeHashing.h
include/llvm/DebugInfo/CodeView/TypeIndex.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/TypeIndexDiscovery.h
include/llvm/DebugInfo/CodeView/TypeRecord.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/CodeView/TypeRecordHelpers.h
include/llvm/DebugInfo/CodeView/TypeRecordMapping.h
include/llvm/DebugInfo/CodeView/TypeStreamMerger.h
include/llvm/DebugInfo/CodeView/TypeSymbolEmitter.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/CodeView/TypeTableCollection.h
include/llvm/DebugInfo/CodeView/TypeVisitorCallbackPipeline.h
include/llvm/DebugInfo/CodeView/TypeVisitorCallbacks.h
include/llvm/DebugInfo/DIContext.h
include/llvm/DebugInfo/DWARF/DWARFAbbreviationDeclaration.h
include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
include/llvm/DebugInfo/DWARF/DWARFAddressRange.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/DWARF/DWARFAttribute.h
include/llvm/DebugInfo/DWARF/DWARFCompileUnit.h
include/llvm/DebugInfo/DWARF/DWARFContext.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h
include/llvm/DebugInfo/DWARF/DWARFDebugAbbrev.h
include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h
include/llvm/DebugInfo/DWARF/DWARFDebugArangeSet.h
include/llvm/DebugInfo/DWARF/DWARFDebugAranges.h
include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h
include/llvm/DebugInfo/DWARF/DWARFDebugInfoEntry.h
include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h
include/llvm/DebugInfo/DWARF/DWARFDebugMacro.h
include/llvm/DebugInfo/DWARF/DWARFDebugPubTable.h
include/llvm/DebugInfo/DWARF/DWARFDebugRangeList.h
include/llvm/DebugInfo/DWARF/DWARFDebugRnglists.h
include/llvm/DebugInfo/DWARF/DWARFDie.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/DWARF/DWARFExpression.h
include/llvm/DebugInfo/DWARF/DWARFFormValue.h
include/llvm/DebugInfo/DWARF/DWARFGdbIndex.h
include/llvm/DebugInfo/DWARF/DWARFListTable.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/DWARF/DWARFObject.h
include/llvm/DebugInfo/DWARF/DWARFRelocMap.h
include/llvm/DebugInfo/DWARF/DWARFSection.h
include/llvm/DebugInfo/DWARF/DWARFTypeUnit.h
include/llvm/DebugInfo/DWARF/DWARFUnit.h
include/llvm/DebugInfo/DWARF/DWARFUnitIndex.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/DWARF/DWARFVerifier.h
include/llvm/DebugInfo/MSF/IMSFFile.h
include/llvm/DebugInfo/MSF/MSFBuilder.h
include/llvm/DebugInfo/MSF/MSFCommon.h
include/llvm/DebugInfo/MSF/MSFError.h
include/llvm/DebugInfo/MSF/MappedBlockStream.h
include/llvm/DebugInfo/PDB/ConcreteSymbolEnumerator.h
include/llvm/DebugInfo/PDB/DIA/DIADataStream.h
include/llvm/DebugInfo/PDB/DIA/DIAEnumDebugStreams.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/PDB/DIA/DIAEnumFrameData.h
include/llvm/DebugInfo/PDB/DIA/DIAEnumInjectedSources.h
include/llvm/DebugInfo/PDB/DIA/DIAEnumLineNumbers.h
include/llvm/DebugInfo/PDB/DIA/DIAEnumSectionContribs.h
include/llvm/DebugInfo/PDB/DIA/DIAEnumSourceFiles.h
include/llvm/DebugInfo/PDB/DIA/DIAEnumSymbols.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/PDB/DIA/DIAEnumTables.h
include/llvm/DebugInfo/PDB/DIA/DIAError.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/PDB/DIA/DIAFrameData.h
include/llvm/DebugInfo/PDB/DIA/DIAInjectedSource.h
include/llvm/DebugInfo/PDB/DIA/DIALineNumber.h
include/llvm/DebugInfo/PDB/DIA/DIARawSymbol.h
include/llvm/DebugInfo/PDB/DIA/DIASectionContrib.h
include/llvm/DebugInfo/PDB/DIA/DIASession.h
include/llvm/DebugInfo/PDB/DIA/DIASourceFile.h
include/llvm/DebugInfo/PDB/DIA/DIASupport.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/PDB/DIA/DIATable.h
include/llvm/DebugInfo/PDB/DIA/DIAUtils.h
include/llvm/DebugInfo/PDB/GenericError.h
include/llvm/DebugInfo/PDB/IPDBDataStream.h
include/llvm/DebugInfo/PDB/IPDBEnumChildren.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/PDB/IPDBFrameData.h
include/llvm/DebugInfo/PDB/IPDBInjectedSource.h
include/llvm/DebugInfo/PDB/IPDBLineNumber.h
include/llvm/DebugInfo/PDB/IPDBRawSymbol.h
include/llvm/DebugInfo/PDB/IPDBSectionContrib.h
include/llvm/DebugInfo/PDB/IPDBSession.h
include/llvm/DebugInfo/PDB/IPDBSourceFile.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/PDB/IPDBTable.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/PDB/Native/DbiModuleDescriptor.h
include/llvm/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.h
include/llvm/DebugInfo/PDB/Native/DbiModuleList.h
include/llvm/DebugInfo/PDB/Native/DbiStream.h
include/llvm/DebugInfo/PDB/Native/DbiStreamBuilder.h
include/llvm/DebugInfo/PDB/Native/EnumTables.h
include/llvm/DebugInfo/PDB/Native/Formatters.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/PDB/Native/GSIStreamBuilder.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/PDB/Native/GlobalsStream.h
include/llvm/DebugInfo/PDB/Native/Hash.h
include/llvm/DebugInfo/PDB/Native/HashTable.h
include/llvm/DebugInfo/PDB/Native/ISectionContribVisitor.h
include/llvm/DebugInfo/PDB/Native/InfoStream.h
include/llvm/DebugInfo/PDB/Native/InfoStreamBuilder.h
include/llvm/DebugInfo/PDB/Native/ModuleDebugStream.h
include/llvm/DebugInfo/PDB/Native/NamedStreamMap.h
include/llvm/DebugInfo/PDB/Native/NativeCompilandSymbol.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/PDB/Native/NativeEnumGlobals.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/PDB/Native/NativeEnumModules.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/DebugInfo/PDB/Native/NativeEnumTypes.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/PDB/Native/NativeExeSymbol.h
include/llvm/DebugInfo/PDB/Native/NativeRawSymbol.h
include/llvm/DebugInfo/PDB/Native/NativeSession.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/PDB/Native/NativeSymbolEnumerator.h
include/llvm/DebugInfo/PDB/Native/NativeTypeArray.h
include/llvm/DebugInfo/PDB/Native/NativeTypeBuiltin.h
include/llvm/DebugInfo/PDB/Native/NativeTypeEnum.h
include/llvm/DebugInfo/PDB/Native/NativeTypeFunctionSig.h
include/llvm/DebugInfo/PDB/Native/NativeTypePointer.h
include/llvm/DebugInfo/PDB/Native/NativeTypeTypedef.h
include/llvm/DebugInfo/PDB/Native/NativeTypeUDT.h
include/llvm/DebugInfo/PDB/Native/NativeTypeVTShape.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/PDB/Native/PDBFile.h
include/llvm/DebugInfo/PDB/Native/PDBFileBuilder.h
include/llvm/DebugInfo/PDB/Native/PDBStringTable.h
include/llvm/DebugInfo/PDB/Native/PDBStringTableBuilder.h
include/llvm/DebugInfo/PDB/Native/PublicsStream.h
include/llvm/DebugInfo/PDB/Native/RawConstants.h
include/llvm/DebugInfo/PDB/Native/RawError.h
include/llvm/DebugInfo/PDB/Native/RawTypes.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/DebugInfo/PDB/Native/SymbolCache.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/PDB/Native/SymbolStream.h
include/llvm/DebugInfo/PDB/Native/TpiHashing.h
include/llvm/DebugInfo/PDB/Native/TpiStream.h
include/llvm/DebugInfo/PDB/Native/TpiStreamBuilder.h
include/llvm/DebugInfo/PDB/PDB.h
include/llvm/DebugInfo/PDB/PDBContext.h
include/llvm/DebugInfo/PDB/PDBExtras.h
include/llvm/DebugInfo/PDB/PDBSymDumper.h
include/llvm/DebugInfo/PDB/PDBSymbol.h
include/llvm/DebugInfo/PDB/PDBSymbolAnnotation.h
include/llvm/DebugInfo/PDB/PDBSymbolBlock.h
include/llvm/DebugInfo/PDB/PDBSymbolCompiland.h
include/llvm/DebugInfo/PDB/PDBSymbolCompilandDetails.h
include/llvm/DebugInfo/PDB/PDBSymbolCompilandEnv.h
include/llvm/DebugInfo/PDB/PDBSymbolCustom.h
include/llvm/DebugInfo/PDB/PDBSymbolData.h
include/llvm/DebugInfo/PDB/PDBSymbolExe.h
include/llvm/DebugInfo/PDB/PDBSymbolFunc.h
include/llvm/DebugInfo/PDB/PDBSymbolFuncDebugEnd.h
include/llvm/DebugInfo/PDB/PDBSymbolFuncDebugStart.h
include/llvm/DebugInfo/PDB/PDBSymbolLabel.h
include/llvm/DebugInfo/PDB/PDBSymbolPublicSymbol.h
include/llvm/DebugInfo/PDB/PDBSymbolThunk.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeArray.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeBaseClass.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeBuiltin.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeCustom.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeDimension.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeEnum.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeFriend.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeFunctionArg.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeFunctionSig.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeManaged.h
include/llvm/DebugInfo/PDB/PDBSymbolTypePointer.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeTypedef.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeUDT.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeVTable.h
include/llvm/DebugInfo/PDB/PDBSymbolTypeVTableShape.h
include/llvm/DebugInfo/PDB/PDBSymbolUnknown.h
include/llvm/DebugInfo/PDB/PDBSymbolUsingNamespace.h
include/llvm/DebugInfo/PDB/PDBTypes.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/DebugInfo/PDB/UDTLayout.h
include/llvm/DebugInfo/Symbolize/DIPrinter.h
include/llvm/DebugInfo/Symbolize/SymbolizableModule.h
include/llvm/DebugInfo/Symbolize/Symbolize.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Demangle/Compiler.h
include/llvm/Demangle/Demangle.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Demangle/ItaniumDemangle.h
include/llvm/Demangle/MicrosoftDemangle.h
include/llvm/Demangle/MicrosoftDemangleNodes.h
include/llvm/Demangle/StringView.h
include/llvm/Demangle/Utility.h
include/llvm/ExecutionEngine/ExecutionEngine.h
include/llvm/ExecutionEngine/GenericValue.h
include/llvm/ExecutionEngine/Interpreter.h
include/llvm/ExecutionEngine/JITEventListener.h
include/llvm/ExecutionEngine/JITSymbol.h
include/llvm/ExecutionEngine/MCJIT.h
include/llvm/ExecutionEngine/OProfileWrapper.h
include/llvm/ExecutionEngine/ObjectCache.h
include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h
include/llvm/ExecutionEngine/Orc/CompileUtils.h
include/llvm/ExecutionEngine/Orc/Core.h
include/llvm/ExecutionEngine/Orc/ExecutionUtils.h
include/llvm/ExecutionEngine/Orc/GlobalMappingLayer.h
include/llvm/ExecutionEngine/Orc/IRCompileLayer.h
include/llvm/ExecutionEngine/Orc/IRTransformLayer.h
include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
include/llvm/ExecutionEngine/Orc/LLJIT.h
include/llvm/ExecutionEngine/Orc/LambdaResolver.h
include/llvm/ExecutionEngine/Orc/Layer.h
include/llvm/ExecutionEngine/Orc/LazyEmittingLayer.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/ExecutionEngine/Orc/LazyReexports.h
include/llvm/ExecutionEngine/Orc/Legacy.h
include/llvm/ExecutionEngine/Orc/NullResolver.h
include/llvm/ExecutionEngine/Orc/ObjectTransformLayer.h
include/llvm/ExecutionEngine/Orc/OrcABISupport.h
include/llvm/ExecutionEngine/Orc/OrcError.h
include/llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h
include/llvm/ExecutionEngine/Orc/OrcRemoteTargetRPCAPI.h
include/llvm/ExecutionEngine/Orc/OrcRemoteTargetServer.h
include/llvm/ExecutionEngine/Orc/RPCSerialization.h
include/llvm/ExecutionEngine/Orc/RPCUtils.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h
include/llvm/ExecutionEngine/Orc/RawByteChannel.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/ExecutionEngine/Orc/RemoteObjectLayer.h
include/llvm/ExecutionEngine/Orc/SymbolStringPool.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/ExecutionEngine/Orc/ThreadSafeModule.h
include/llvm/ExecutionEngine/OrcMCJITReplacement.h
include/llvm/ExecutionEngine/RTDyldMemoryManager.h
include/llvm/ExecutionEngine/RuntimeDyld.h
include/llvm/ExecutionEngine/RuntimeDyldChecker.h
include/llvm/ExecutionEngine/SectionMemoryManager.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/FuzzMutate/FuzzerCLI.h
include/llvm/FuzzMutate/IRMutator.h
include/llvm/FuzzMutate/OpDescriptor.h
include/llvm/FuzzMutate/Operations.h
include/llvm/FuzzMutate/Random.h
include/llvm/FuzzMutate/RandomIRBuilder.h
include/llvm/IR/Argument.h
include/llvm/IR/AssemblyAnnotationWriter.h
include/llvm/IR/Attributes.h
include/llvm/IR/Attributes.inc
include/llvm/IR/Attributes.td
include/llvm/IR/AutoUpgrade.h
include/llvm/IR/BasicBlock.h
include/llvm/IR/CFG.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/IR/CFGDiff.h
include/llvm/IR/CallSite.h
include/llvm/IR/CallingConv.h
include/llvm/IR/Comdat.h
include/llvm/IR/Constant.h
include/llvm/IR/ConstantFolder.h
include/llvm/IR/ConstantRange.h
include/llvm/IR/Constants.h
include/llvm/IR/DIBuilder.h
include/llvm/IR/DataLayout.h
include/llvm/IR/DebugInfo.h
include/llvm/IR/DebugInfoFlags.def
include/llvm/IR/DebugInfoMetadata.h
include/llvm/IR/DebugLoc.h
include/llvm/IR/DerivedTypes.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/IR/DerivedUser.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/IR/DiagnosticHandler.h
include/llvm/IR/DiagnosticInfo.h
include/llvm/IR/DiagnosticPrinter.h
include/llvm/IR/DomTreeUpdater.h
include/llvm/IR/Dominators.h
include/llvm/IR/Function.h
include/llvm/IR/GVMaterializer.h
include/llvm/IR/GetElementPtrTypeIterator.h
include/llvm/IR/GlobalAlias.h
include/llvm/IR/GlobalIFunc.h
include/llvm/IR/GlobalIndirectSymbol.h
include/llvm/IR/GlobalObject.h
include/llvm/IR/GlobalValue.h
include/llvm/IR/GlobalVariable.h
include/llvm/IR/IRBuilder.h
include/llvm/IR/IRPrintingPasses.h
include/llvm/IR/InlineAsm.h
include/llvm/IR/InstIterator.h
include/llvm/IR/InstVisitor.h
include/llvm/IR/InstrTypes.h
include/llvm/IR/Instruction.def
include/llvm/IR/Instruction.h
include/llvm/IR/Instructions.h
include/llvm/IR/IntrinsicEnums.inc
include/llvm/IR/IntrinsicImpl.inc
include/llvm/IR/IntrinsicInst.h
include/llvm/IR/Intrinsics.h
include/llvm/IR/Intrinsics.td
include/llvm/IR/IntrinsicsAArch64.td
include/llvm/IR/IntrinsicsAMDGPU.td
include/llvm/IR/IntrinsicsARM.td
include/llvm/IR/IntrinsicsBPF.td
include/llvm/IR/IntrinsicsHexagon.td
include/llvm/IR/IntrinsicsMips.td
include/llvm/IR/IntrinsicsNVVM.td
include/llvm/IR/IntrinsicsPowerPC.td
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/IR/IntrinsicsRISCV.td
include/llvm/IR/IntrinsicsSystemZ.td
include/llvm/IR/IntrinsicsWebAssembly.td
include/llvm/IR/IntrinsicsX86.td
include/llvm/IR/IntrinsicsXCore.td
include/llvm/IR/LLVMContext.h
include/llvm/IR/LegacyPassManager.h
include/llvm/IR/LegacyPassManagers.h
include/llvm/IR/LegacyPassNameParser.h
include/llvm/IR/MDBuilder.h
include/llvm/IR/Mangler.h
include/llvm/IR/Metadata.def
include/llvm/IR/Metadata.h
include/llvm/IR/Module.h
include/llvm/IR/ModuleSlotTracker.h
include/llvm/IR/ModuleSummaryIndex.h
include/llvm/IR/ModuleSummaryIndexYAML.h
include/llvm/IR/NoFolder.h
include/llvm/IR/OperandTraits.h
include/llvm/IR/Operator.h
include/llvm/IR/OptBisect.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/IR/PassInstrumentation.h
include/llvm/IR/PassManager.h
include/llvm/IR/PassManagerInternal.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/IR/PassTimingInfo.h
include/llvm/IR/PatternMatch.h
include/llvm/IR/PredIteratorCache.h
include/llvm/IR/ProfileSummary.h
include/llvm/IR/RuntimeLibcalls.def
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/IR/SafepointIRVerifier.h
include/llvm/IR/Statepoint.h
include/llvm/IR/SymbolTableListTraits.h
include/llvm/IR/TrackingMDRef.h
include/llvm/IR/Type.h
include/llvm/IR/TypeFinder.h
include/llvm/IR/Use.h
include/llvm/IR/UseListOrder.h
include/llvm/IR/User.h
include/llvm/IR/Value.def
include/llvm/IR/Value.h
include/llvm/IR/ValueHandle.h
include/llvm/IR/ValueMap.h
include/llvm/IR/ValueSymbolTable.h
include/llvm/IR/Verifier.h
include/llvm/IRReader/IRReader.h
include/llvm/InitializePasses.h
include/llvm/LTO/Caching.h
include/llvm/LTO/Config.h
include/llvm/LTO/LTO.h
include/llvm/LTO/LTOBackend.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/LTO/SummaryBasedOptimizations.h
include/llvm/LTO/legacy/LTOCodeGenerator.h
include/llvm/LTO/legacy/LTOModule.h
include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
include/llvm/LTO/legacy/UpdateCompilerUsed.h
include/llvm/LineEditor/LineEditor.h
include/llvm/LinkAllIR.h
include/llvm/LinkAllPasses.h
include/llvm/Linker/IRMover.h
include/llvm/Linker/Linker.h
include/llvm/MC/ConstantPools.h
include/llvm/MC/LaneBitmask.h
include/llvm/MC/MCAsmBackend.h
include/llvm/MC/MCAsmInfo.h
include/llvm/MC/MCAsmInfoCOFF.h
include/llvm/MC/MCAsmInfoDarwin.h
include/llvm/MC/MCAsmInfoELF.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/MC/MCAsmInfoWasm.h
include/llvm/MC/MCAsmLayout.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/MC/MCAsmMacro.h
include/llvm/MC/MCAssembler.h
include/llvm/MC/MCCodeEmitter.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/MC/MCCodePadder.h
include/llvm/MC/MCCodeView.h
include/llvm/MC/MCContext.h
include/llvm/MC/MCDirectives.h
include/llvm/MC/MCDisassembler/MCDisassembler.h
include/llvm/MC/MCDisassembler/MCExternalSymbolizer.h
include/llvm/MC/MCDisassembler/MCRelocationInfo.h
include/llvm/MC/MCDisassembler/MCSymbolizer.h
include/llvm/MC/MCDwarf.h
include/llvm/MC/MCELFObjectWriter.h
include/llvm/MC/MCELFStreamer.h
include/llvm/MC/MCExpr.h
include/llvm/MC/MCFixedLenDisassembler.h
include/llvm/MC/MCFixup.h
include/llvm/MC/MCFixupKindInfo.h
include/llvm/MC/MCFragment.h
include/llvm/MC/MCInst.h
include/llvm/MC/MCInstBuilder.h
include/llvm/MC/MCInstPrinter.h
include/llvm/MC/MCInstrAnalysis.h
include/llvm/MC/MCInstrDesc.h
include/llvm/MC/MCInstrInfo.h
include/llvm/MC/MCInstrItineraries.h
include/llvm/MC/MCLabel.h
include/llvm/MC/MCLinkerOptimizationHint.h
include/llvm/MC/MCMachObjectWriter.h
include/llvm/MC/MCObjectFileInfo.h
include/llvm/MC/MCObjectStreamer.h
include/llvm/MC/MCObjectWriter.h
include/llvm/MC/MCParser/AsmCond.h
include/llvm/MC/MCParser/AsmLexer.h
include/llvm/MC/MCParser/MCAsmLexer.h
include/llvm/MC/MCParser/MCAsmParser.h
include/llvm/MC/MCParser/MCAsmParserExtension.h
include/llvm/MC/MCParser/MCAsmParserUtils.h
include/llvm/MC/MCParser/MCParsedAsmOperand.h
include/llvm/MC/MCParser/MCTargetAsmParser.h
include/llvm/MC/MCRegisterInfo.h
include/llvm/MC/MCSchedule.h
include/llvm/MC/MCSection.h
include/llvm/MC/MCSectionCOFF.h
include/llvm/MC/MCSectionELF.h
include/llvm/MC/MCSectionMachO.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/MC/MCSectionWasm.h
include/llvm/MC/MCStreamer.h
include/llvm/MC/MCSubtargetInfo.h
include/llvm/MC/MCSymbol.h
include/llvm/MC/MCSymbolCOFF.h
include/llvm/MC/MCSymbolELF.h
include/llvm/MC/MCSymbolMachO.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/MC/MCSymbolWasm.h
include/llvm/MC/MCTargetOptions.h
include/llvm/MC/MCTargetOptionsCommandFlags.inc
include/llvm/MC/MCValue.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/MC/MCWasmObjectWriter.h
include/llvm/MC/MCWasmStreamer.h
include/llvm/MC/MCWin64EH.h
include/llvm/MC/MCWinCOFFObjectWriter.h
include/llvm/MC/MCWinCOFFStreamer.h
include/llvm/MC/MCWinEH.h
include/llvm/MC/MachineLocation.h
include/llvm/MC/SectionKind.h
include/llvm/MC/StringTableBuilder.h
include/llvm/MC/SubtargetFeature.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/MCA/Context.h
include/llvm/MCA/HWEventListener.h
include/llvm/MCA/HardwareUnits/HardwareUnit.h
include/llvm/MCA/HardwareUnits/LSUnit.h
include/llvm/MCA/HardwareUnits/RegisterFile.h
include/llvm/MCA/HardwareUnits/ResourceManager.h
include/llvm/MCA/HardwareUnits/RetireControlUnit.h
include/llvm/MCA/HardwareUnits/Scheduler.h
include/llvm/MCA/InstrBuilder.h
include/llvm/MCA/Instruction.h
include/llvm/MCA/Pipeline.h
include/llvm/MCA/SourceMgr.h
include/llvm/MCA/Stages/DispatchStage.h
include/llvm/MCA/Stages/EntryStage.h
include/llvm/MCA/Stages/ExecuteStage.h
include/llvm/MCA/Stages/InstructionTables.h
include/llvm/MCA/Stages/RetireStage.h
include/llvm/MCA/Stages/Stage.h
include/llvm/MCA/Support.h
include/llvm/Object/Archive.h
include/llvm/Object/ArchiveWriter.h
include/llvm/Object/Binary.h
include/llvm/Object/COFF.h
include/llvm/Object/COFFImportFile.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Object/COFFModuleDefinition.h
include/llvm/Object/CVDebugRecord.h
include/llvm/Object/Decompressor.h
include/llvm/Object/ELF.h
include/llvm/Object/ELFObjectFile.h
include/llvm/Object/ELFTypes.h
include/llvm/Object/Error.h
include/llvm/Object/IRObjectFile.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Object/IRSymtab.h
include/llvm/Object/MachO.h
include/llvm/Object/MachOUniversal.h
include/llvm/Object/ModuleSymbolTable.h
include/llvm/Object/ObjectFile.h
include/llvm/Object/RelocVisitor.h
include/llvm/Object/StackMapParser.h
include/llvm/Object/SymbolSize.h
include/llvm/Object/SymbolicFile.h
include/llvm/Object/Wasm.h
include/llvm/Object/WasmTraits.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Object/WindowsResource.h
include/llvm/ObjectYAML/COFFYAML.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/ObjectYAML/CodeViewYAMLDebugSections.h
include/llvm/ObjectYAML/CodeViewYAMLSymbols.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/ObjectYAML/CodeViewYAMLTypeHashing.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/ObjectYAML/CodeViewYAMLTypes.h
include/llvm/ObjectYAML/DWARFEmitter.h
include/llvm/ObjectYAML/DWARFYAML.h
include/llvm/ObjectYAML/ELFYAML.h
include/llvm/ObjectYAML/MachOYAML.h
include/llvm/ObjectYAML/ObjectYAML.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/ObjectYAML/WasmYAML.h
include/llvm/ObjectYAML/YAML.h
include/llvm/Option/Arg.h
include/llvm/Option/ArgList.h
include/llvm/Option/OptParser.td
include/llvm/Option/OptSpecifier.h
include/llvm/Option/OptTable.h
include/llvm/Option/Option.h
include/llvm/Pass.h
include/llvm/PassAnalysisSupport.h
include/llvm/PassInfo.h
include/llvm/PassRegistry.h
include/llvm/PassSupport.h
include/llvm/Passes/PassBuilder.h
include/llvm/Passes/PassPlugin.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Passes/StandardInstrumentations.h
include/llvm/ProfileData/Coverage/CoverageMapping.h
include/llvm/ProfileData/Coverage/CoverageMappingReader.h
include/llvm/ProfileData/Coverage/CoverageMappingWriter.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/ProfileData/GCOV.h
include/llvm/ProfileData/InstrProf.h
include/llvm/ProfileData/InstrProfData.inc
include/llvm/ProfileData/InstrProfReader.h
include/llvm/ProfileData/InstrProfWriter.h
include/llvm/ProfileData/ProfileCommon.h
include/llvm/ProfileData/SampleProf.h
include/llvm/ProfileData/SampleProfReader.h
include/llvm/ProfileData/SampleProfWriter.h
include/llvm/Support/AArch64TargetParser.def
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/AArch64TargetParser.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Support/AMDGPUMetadata.h
include/llvm/Support/AMDHSAKernelDescriptor.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/ARMAttributeParser.h
include/llvm/Support/ARMBuildAttributes.h
include/llvm/Support/ARMEHABI.h
include/llvm/Support/ARMTargetParser.def
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/ARMTargetParser.h
include/llvm/Support/ARMWinEH.h
include/llvm/Support/AlignOf.h
include/llvm/Support/Allocator.h
include/llvm/Support/ArrayRecycler.h
include/llvm/Support/Atomic.h
include/llvm/Support/AtomicOrdering.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/BinaryByteStream.h
include/llvm/Support/BinaryItemStream.h
include/llvm/Support/BinaryStream.h
include/llvm/Support/BinaryStreamArray.h
include/llvm/Support/BinaryStreamError.h
include/llvm/Support/BinaryStreamReader.h
include/llvm/Support/BinaryStreamRef.h
include/llvm/Support/BinaryStreamWriter.h
include/llvm/Support/BlockFrequency.h
include/llvm/Support/BranchProbability.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/BuryPointer.h
include/llvm/Support/CBindingWrapping.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/CFGUpdate.h
include/llvm/Support/COM.h
include/llvm/Support/CachePruning.h
include/llvm/Support/Capacity.h
include/llvm/Support/Casting.h
include/llvm/Support/CheckedArithmetic.h
include/llvm/Support/Chrono.h
include/llvm/Support/CodeGen.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Support/CodeGenCoverage.h
include/llvm/Support/CommandLine.h
include/llvm/Support/Compiler.h
include/llvm/Support/Compression.h
include/llvm/Support/ConvertUTF.h
include/llvm/Support/CrashRecoveryContext.h
include/llvm/Support/DJB.h
include/llvm/Support/DOTGraphTraits.h
include/llvm/Support/DataExtractor.h
include/llvm/Support/DataTypes.h
include/llvm/Support/Debug.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/DebugCounter.h
include/llvm/Support/DynamicLibrary.h
include/llvm/Support/Endian.h
include/llvm/Support/EndianStream.h
include/llvm/Support/Errc.h
include/llvm/Support/Errno.h
include/llvm/Support/Error.h
include/llvm/Support/ErrorHandling.h
include/llvm/Support/ErrorOr.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/FileCheck.h
include/llvm/Support/FileOutputBuffer.h
include/llvm/Support/FileSystem.h
include/llvm/Support/FileUtilities.h
include/llvm/Support/Format.h
include/llvm/Support/FormatAdapters.h
include/llvm/Support/FormatCommon.h
include/llvm/Support/FormatProviders.h
include/llvm/Support/FormatVariadic.h
include/llvm/Support/FormatVariadicDetails.h
include/llvm/Support/FormattedStream.h
include/llvm/Support/GenericDomTree.h
include/llvm/Support/GenericDomTreeConstruction.h
include/llvm/Support/GlobPattern.h
include/llvm/Support/GraphWriter.h
include/llvm/Support/Host.h
include/llvm/Support/InitLLVM.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/ItaniumManglingCanonicalizer.h
include/llvm/Support/JSON.h
include/llvm/Support/JamCRC.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/KnownBits.h
include/llvm/Support/LEB128.h
include/llvm/Support/LICENSE.TXT
include/llvm/Support/LineIterator.h
include/llvm/Support/Locale.h
include/llvm/Support/LockFileManager.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/LowLevelTypeImpl.h
include/llvm/Support/MD5.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/MSVCErrorWorkarounds.h
include/llvm/Support/MachineValueType.h
include/llvm/Support/ManagedStatic.h
include/llvm/Support/MathExtras.h
include/llvm/Support/MemAlloc.h
include/llvm/Support/Memory.h
include/llvm/Support/MemoryBuffer.h
include/llvm/Support/MipsABIFlags.h
include/llvm/Support/Mutex.h
include/llvm/Support/MutexGuard.h
include/llvm/Support/NativeFormatting.h
include/llvm/Support/OnDiskHashTable.h
include/llvm/Support/Options.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/Parallel.h
include/llvm/Support/Path.h
include/llvm/Support/PluginLoader.h
include/llvm/Support/PointerLikeTypeTraits.h
include/llvm/Support/PrettyStackTrace.h
include/llvm/Support/Printable.h
include/llvm/Support/Process.h
include/llvm/Support/Program.h
include/llvm/Support/RWMutex.h
include/llvm/Support/RandomNumberGenerator.h
include/llvm/Support/Recycler.h
include/llvm/Support/RecyclingAllocator.h
include/llvm/Support/Regex.h
include/llvm/Support/Registry.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/ReverseIteration.h
include/llvm/Support/SHA1.h
include/llvm/Support/SMLoc.h
include/llvm/Support/SaveAndRestore.h
include/llvm/Support/ScaledNumber.h
include/llvm/Support/ScopedPrinter.h
include/llvm/Support/Signals.h
include/llvm/Support/SmallVectorMemoryBuffer.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/Solaris/sys/regset.h
include/llvm/Support/SourceMgr.h
include/llvm/Support/SpecialCaseList.h
include/llvm/Support/StringPool.h
include/llvm/Support/StringSaver.h
include/llvm/Support/SwapByteOrder.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/SymbolRemappingReader.h
include/llvm/Support/SystemUtils.h
include/llvm/Support/TarWriter.h
include/llvm/Support/TargetOpcodes.def
include/llvm/Support/TargetParser.h
include/llvm/Support/TargetRegistry.h
include/llvm/Support/TargetSelect.h
include/llvm/Support/TaskQueue.h
include/llvm/Support/ThreadLocal.h
include/llvm/Support/ThreadPool.h
include/llvm/Support/Threading.h
include/llvm/Support/Timer.h
include/llvm/Support/ToolOutputFile.h
include/llvm/Support/TrailingObjects.h
include/llvm/Support/TrigramIndex.h
include/llvm/Support/TypeName.h
include/llvm/Support/Unicode.h
include/llvm/Support/UnicodeCharRanges.h
include/llvm/Support/UniqueLock.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Support/VCSRevision.h
include/llvm/Support/Valgrind.h
include/llvm/Support/VersionTuple.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Support/VirtualFileSystem.h
include/llvm/Support/Watchdog.h
include/llvm/Support/Win64EH.h
include/llvm/Support/WindowsError.h
include/llvm/Support/WithColor.h
include/llvm/Support/X86DisassemblerDecoderCommon.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Support/X86TargetParser.def
include/llvm/Support/YAMLParser.h
include/llvm/Support/YAMLTraits.h
include/llvm/Support/circular_raw_ostream.h
include/llvm/Support/raw_os_ostream.h
include/llvm/Support/raw_ostream.h
include/llvm/Support/raw_sha1_ostream.h
include/llvm/Support/thread.h
include/llvm/Support/type_traits.h
include/llvm/Support/xxhash.h
include/llvm/TableGen/Error.h
include/llvm/TableGen/Main.h
include/llvm/TableGen/Record.h
include/llvm/TableGen/SearchableTable.td
include/llvm/TableGen/SetTheory.h
include/llvm/TableGen/StringMatcher.h
include/llvm/TableGen/StringToOffsetTable.h
include/llvm/TableGen/TableGenBackend.h
include/llvm/Target/CodeGenCWrappers.h
include/llvm/Target/GenericOpcodes.td
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Target/GlobalISel/RegisterBank.td
include/llvm/Target/GlobalISel/SelectionDAGCompat.td
include/llvm/Target/GlobalISel/Target.td
include/llvm/Target/Target.td
include/llvm/Target/TargetCallingConv.td
include/llvm/Target/TargetInstrPredicate.td
include/llvm/Target/TargetIntrinsicInfo.h
include/llvm/Target/TargetItinerary.td
include/llvm/Target/TargetLoweringObjectFile.h
include/llvm/Target/TargetMachine.h
include/llvm/Target/TargetOptions.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Target/TargetPfmCounters.td
include/llvm/Target/TargetSchedule.td
include/llvm/Target/TargetSelectionDAG.td
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Testing/Support/Error.h
include/llvm/Testing/Support/SupportHelpers.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/TextAPI/ELF/ELFStub.h
include/llvm/TextAPI/ELF/TBEHandler.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/ToolDrivers/llvm-dlltool/DlltoolDriver.h
include/llvm/ToolDrivers/llvm-lib/LibDriver.h
include/llvm/Transforms/AggressiveInstCombine/AggressiveInstCombine.h
include/llvm/Transforms/Coroutines.h
include/llvm/Transforms/IPO.h
include/llvm/Transforms/IPO/AlwaysInliner.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/IPO/ArgumentPromotion.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/IPO/CalledValuePropagation.h
include/llvm/Transforms/IPO/ConstantMerge.h
include/llvm/Transforms/IPO/CrossDSOCFI.h
include/llvm/Transforms/IPO/DeadArgumentElimination.h
include/llvm/Transforms/IPO/ElimAvailExtern.h
include/llvm/Transforms/IPO/ForceFunctionAttrs.h
include/llvm/Transforms/IPO/FunctionAttrs.h
include/llvm/Transforms/IPO/FunctionImport.h
include/llvm/Transforms/IPO/GlobalDCE.h
include/llvm/Transforms/IPO/GlobalOpt.h
include/llvm/Transforms/IPO/GlobalSplit.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/IPO/HotColdSplitting.h
include/llvm/Transforms/IPO/InferFunctionAttrs.h
include/llvm/Transforms/IPO/Inliner.h
include/llvm/Transforms/IPO/Internalize.h
include/llvm/Transforms/IPO/LowerTypeTests.h
include/llvm/Transforms/IPO/PartialInlining.h
include/llvm/Transforms/IPO/PassManagerBuilder.h
include/llvm/Transforms/IPO/SCCP.h
include/llvm/Transforms/IPO/SampleProfile.h
include/llvm/Transforms/IPO/StripDeadPrototypes.h
include/llvm/Transforms/IPO/SyntheticCountsPropagation.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/IPO/ThinLTOBitcodeWriter.h
include/llvm/Transforms/IPO/WholeProgramDevirt.h
include/llvm/Transforms/InstCombine/InstCombine.h
include/llvm/Transforms/InstCombine/InstCombineWorklist.h
include/llvm/Transforms/Instrumentation.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/Instrumentation/BoundsChecking.h
include/llvm/Transforms/Instrumentation/CGProfile.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Instrumentation/ControlHeightReduction.h
include/llvm/Transforms/Instrumentation/GCOVProfiler.h
include/llvm/Transforms/Instrumentation/InstrProfiling.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Instrumentation/MemorySanitizer.h
include/llvm/Transforms/Instrumentation/PGOInstrumentation.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Instrumentation/ThreadSanitizer.h
include/llvm/Transforms/ObjCARC.h
include/llvm/Transforms/Scalar.h
include/llvm/Transforms/Scalar/ADCE.h
include/llvm/Transforms/Scalar/AlignmentFromAssumptions.h
include/llvm/Transforms/Scalar/BDCE.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/Scalar/CallSiteSplitting.h
include/llvm/Transforms/Scalar/ConstantHoisting.h
include/llvm/Transforms/Scalar/CorrelatedValuePropagation.h
include/llvm/Transforms/Scalar/DCE.h
include/llvm/Transforms/Scalar/DeadStoreElimination.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/Scalar/DivRemPairs.h
include/llvm/Transforms/Scalar/EarlyCSE.h
include/llvm/Transforms/Scalar/Float2Int.h
include/llvm/Transforms/Scalar/GVN.h
include/llvm/Transforms/Scalar/GVNExpression.h
include/llvm/Transforms/Scalar/GuardWidening.h
include/llvm/Transforms/Scalar/IVUsersPrinter.h
include/llvm/Transforms/Scalar/IndVarSimplify.h
include/llvm/Transforms/Scalar/InductiveRangeCheckElimination.h
include/llvm/Transforms/Scalar/InstSimplifyPass.h
include/llvm/Transforms/Scalar/JumpThreading.h
include/llvm/Transforms/Scalar/LICM.h
include/llvm/Transforms/Scalar/LoopAccessAnalysisPrinter.h
include/llvm/Transforms/Scalar/LoopDataPrefetch.h
include/llvm/Transforms/Scalar/LoopDeletion.h
include/llvm/Transforms/Scalar/LoopDistribute.h
include/llvm/Transforms/Scalar/LoopIdiomRecognize.h
include/llvm/Transforms/Scalar/LoopInstSimplify.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/Scalar/LoopLoadElimination.h
include/llvm/Transforms/Scalar/LoopPassManager.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/Scalar/LoopPredication.h
include/llvm/Transforms/Scalar/LoopRotation.h
include/llvm/Transforms/Scalar/LoopSimplifyCFG.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/Scalar/LoopSink.h
include/llvm/Transforms/Scalar/LoopStrengthReduce.h
include/llvm/Transforms/Scalar/LoopUnrollAndJamPass.h
include/llvm/Transforms/Scalar/LoopUnrollPass.h
include/llvm/Transforms/Scalar/LowerAtomic.h
include/llvm/Transforms/Scalar/LowerExpectIntrinsic.h
include/llvm/Transforms/Scalar/LowerGuardIntrinsic.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Scalar/MakeGuardsExplicit.h
include/llvm/Transforms/Scalar/MemCpyOptimizer.h
include/llvm/Transforms/Scalar/MergedLoadStoreMotion.h
include/llvm/Transforms/Scalar/NaryReassociate.h
include/llvm/Transforms/Scalar/NewGVN.h
include/llvm/Transforms/Scalar/PartiallyInlineLibCalls.h
include/llvm/Transforms/Scalar/Reassociate.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/Scalar/RewriteStatepointsForGC.h
include/llvm/Transforms/Scalar/SCCP.h
include/llvm/Transforms/Scalar/SROA.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Scalar/Scalarizer.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/Scalar/SimpleLoopUnswitch.h
include/llvm/Transforms/Scalar/SimplifyCFG.h
include/llvm/Transforms/Scalar/Sink.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/Scalar/SpeculateAroundPHIs.h
include/llvm/Transforms/Scalar/SpeculativeExecution.h
include/llvm/Transforms/Scalar/TailRecursionElimination.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Scalar/WarnMissedTransforms.h
include/llvm/Transforms/Utils.h
include/llvm/Transforms/Utils/ASanStackFrameLayout.h
include/llvm/Transforms/Utils/AddDiscriminators.h
include/llvm/Transforms/Utils/BasicBlockUtils.h
include/llvm/Transforms/Utils/BreakCriticalEdges.h
include/llvm/Transforms/Utils/BuildLibCalls.h
include/llvm/Transforms/Utils/BypassSlowDivision.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/Utils/CallPromotionUtils.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Utils/CanonicalizeAliases.h
include/llvm/Transforms/Utils/Cloning.h
include/llvm/Transforms/Utils/CodeExtractor.h
include/llvm/Transforms/Utils/CtorUtils.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/Transforms/Utils/EntryExitInstrumenter.h
include/llvm/Transforms/Utils/EscapeEnumerator.h
include/llvm/Transforms/Utils/Evaluator.h
include/llvm/Transforms/Utils/FunctionComparator.h
include/llvm/Transforms/Utils/FunctionImportUtils.h
include/llvm/Transforms/Utils/GlobalStatus.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Utils/GuardUtils.h
include/llvm/Transforms/Utils/ImportedFunctionsInliningStatistics.h
include/llvm/Transforms/Utils/IntegerDivision.h
include/llvm/Transforms/Utils/LCSSA.h
include/llvm/Transforms/Utils/LibCallsShrinkWrap.h
include/llvm/Transforms/Utils/Local.h
include/llvm/Transforms/Utils/LoopRotationUtils.h
include/llvm/Transforms/Utils/LoopSimplify.h
include/llvm/Transforms/Utils/LoopUtils.h
include/llvm/Transforms/Utils/LoopVersioning.h
include/llvm/Transforms/Utils/LowerInvoke.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/Utils/LowerMemIntrinsics.h
include/llvm/Transforms/Utils/Mem2Reg.h
include/llvm/Transforms/Utils/ModuleUtils.h
include/llvm/Transforms/Utils/NameAnonGlobals.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/Utils/PredicateInfo.h
include/llvm/Transforms/Utils/PromoteMemToReg.h
include/llvm/Transforms/Utils/SSAUpdater.h
include/llvm/Transforms/Utils/SSAUpdaterBulk.h
include/llvm/Transforms/Utils/SSAUpdaterImpl.h
include/llvm/Transforms/Utils/SanitizerStats.h
include/llvm/Transforms/Utils/SimplifyIndVar.h
include/llvm/Transforms/Utils/SimplifyLibCalls.h
include/llvm/Transforms/Utils/SplitModule.h
include/llvm/Transforms/Utils/SymbolRewriter.h
include/llvm/Transforms/Utils/UnifyFunctionExitNodes.h
include/llvm/Transforms/Utils/UnrollLoop.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/Transforms/Utils/VNCoercion.h
include/llvm/Transforms/Utils/ValueMapper.h
include/llvm/Transforms/Vectorize.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/Transforms/Vectorize/LoadStoreVectorizer.h
include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
include/llvm/Transforms/Vectorize/LoopVectorize.h
include/llvm/Transforms/Vectorize/SLPVectorizer.h
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
include/llvm/WindowsManifest/WindowsManifestMerger.h
include/llvm/WindowsResource/ResourceProcessor.h
include/llvm/WindowsResource/ResourceScriptToken.h
include/llvm/WindowsResource/ResourceScriptTokenList.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/XRay/BlockIndexer.h
include/llvm/XRay/BlockPrinter.h
include/llvm/XRay/BlockVerifier.h
include/llvm/XRay/FDRLogBuilder.h
include/llvm/XRay/FDRRecordConsumer.h
include/llvm/XRay/FDRRecordProducer.h
include/llvm/XRay/FDRRecords.h
include/llvm/XRay/FDRTraceExpander.h
include/llvm/XRay/FDRTraceWriter.h
include/llvm/XRay/FileHeaderReader.h
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
include/llvm/XRay/Graph.h
include/llvm/XRay/InstrumentationMap.h
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
include/llvm/XRay/Profile.h
include/llvm/XRay/RecordPrinter.h
include/llvm/XRay/Trace.h
include/llvm/XRay/XRayRecord.h
include/llvm/XRay/YAMLXRayRecord.h
lib/cmake/llvm/AddLLVM.cmake
lib/cmake/llvm/AddLLVMDefinitions.cmake
lib/cmake/llvm/AddOCaml.cmake
lib/cmake/llvm/AddSphinxTarget.cmake
lib/cmake/llvm/CheckAtomic.cmake
lib/cmake/llvm/CheckCompilerVersion.cmake
lib/cmake/llvm/CheckLinkerFlag.cmake
lib/cmake/llvm/ChooseMSVCCRT.cmake
lib/cmake/llvm/CrossCompile.cmake
lib/cmake/llvm/DetermineGCCCompatible.cmake
lib/cmake/llvm/FindLibpfm.cmake
lib/cmake/llvm/FindOCaml.cmake
lib/cmake/llvm/FindSphinx.cmake
lib/cmake/llvm/GenerateVersionFromCVS.cmake
lib/cmake/llvm/GetSVN.cmake
lib/cmake/llvm/HandleLLVMOptions.cmake
lib/cmake/llvm/HandleLLVMStdlib.cmake
lib/cmake/llvm/LLVM-Config.cmake
lib/cmake/llvm/LLVMConfig.cmake
lib/cmake/llvm/LLVMConfigVersion.cmake
lib/cmake/llvm/LLVMExports-release.cmake
lib/cmake/llvm/LLVMExports.cmake
lib/cmake/llvm/LLVMExternalProjectUtils.cmake
lib/cmake/llvm/LLVMInstallSymlink.cmake
lib/cmake/llvm/LLVMProcessSources.cmake
lib/cmake/llvm/TableGen.cmake
lib/cmake/llvm/VersionFromVCS.cmake
lib/libLLVM-${PKGVERSION}.${SOEXT}
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
lib/libLLVM-8.${SOEXT}
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
lib/libLLVM.${SOEXT}
${PLIST.AArch64}lib/libLLVMAArch64AsmParser.a
${PLIST.AArch64}lib/libLLVMAArch64AsmPrinter.a
${PLIST.AArch64}lib/libLLVMAArch64CodeGen.a
${PLIST.AArch64}lib/libLLVMAArch64Desc.a
${PLIST.AArch64}lib/libLLVMAArch64Disassembler.a
${PLIST.AArch64}lib/libLLVMAArch64Info.a
${PLIST.AArch64}lib/libLLVMAArch64Utils.a
${PLIST.AMDGPU}lib/libLLVMAMDGPUAsmParser.a
${PLIST.AMDGPU}lib/libLLVMAMDGPUAsmPrinter.a
${PLIST.AMDGPU}lib/libLLVMAMDGPUCodeGen.a
${PLIST.AMDGPU}lib/libLLVMAMDGPUDesc.a
${PLIST.AMDGPU}lib/libLLVMAMDGPUDisassembler.a
${PLIST.AMDGPU}lib/libLLVMAMDGPUInfo.a
${PLIST.AMDGPU}lib/libLLVMAMDGPUUtils.a
${PLIST.ARM}lib/libLLVMARMAsmParser.a
${PLIST.ARM}lib/libLLVMARMAsmPrinter.a
${PLIST.ARM}lib/libLLVMARMCodeGen.a
${PLIST.ARM}lib/libLLVMARMDesc.a
${PLIST.ARM}lib/libLLVMARMDisassembler.a
${PLIST.ARM}lib/libLLVMARMInfo.a
${PLIST.ARM}lib/libLLVMARMUtils.a
lib/libLLVMAggressiveInstCombine.a
lib/libLLVMAnalysis.a
lib/libLLVMAsmParser.a
lib/libLLVMAsmPrinter.a
${PLIST.BPF}lib/libLLVMBPFAsmParser.a
${PLIST.BPF}lib/libLLVMBPFAsmPrinter.a
${PLIST.BPF}lib/libLLVMBPFCodeGen.a
${PLIST.BPF}lib/libLLVMBPFDesc.a
${PLIST.BPF}lib/libLLVMBPFDisassembler.a
${PLIST.BPF}lib/libLLVMBPFInfo.a
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
lib/libLLVMBinaryFormat.a
lib/libLLVMBitReader.a
lib/libLLVMBitWriter.a
lib/libLLVMCodeGen.a
lib/libLLVMCore.a
lib/libLLVMCoroutines.a
lib/libLLVMCoverage.a
lib/libLLVMDebugInfoCodeView.a
lib/libLLVMDebugInfoDWARF.a
lib/libLLVMDebugInfoMSF.a
lib/libLLVMDebugInfoPDB.a
lib/libLLVMDemangle.a
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
lib/libLLVMDlltoolDriver.a
lib/libLLVMExecutionEngine.a
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
lib/libLLVMFuzzMutate.a
lib/libLLVMGlobalISel.a
${PLIST.Hexagon}lib/libLLVMHexagonAsmParser.a
${PLIST.Hexagon}lib/libLLVMHexagonCodeGen.a
${PLIST.Hexagon}lib/libLLVMHexagonDesc.a
${PLIST.Hexagon}lib/libLLVMHexagonDisassembler.a
${PLIST.Hexagon}lib/libLLVMHexagonInfo.a
lib/libLLVMIRReader.a
lib/libLLVMInstCombine.a
lib/libLLVMInstrumentation.a
lib/libLLVMInterpreter.a
lib/libLLVMLTO.a
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
${PLIST.Lanai}lib/libLLVMLanaiAsmParser.a
${PLIST.Lanai}lib/libLLVMLanaiAsmPrinter.a
${PLIST.Lanai}lib/libLLVMLanaiCodeGen.a
${PLIST.Lanai}lib/libLLVMLanaiDesc.a
${PLIST.Lanai}lib/libLLVMLanaiDisassembler.a
${PLIST.Lanai}lib/libLLVMLanaiInfo.a
lib/libLLVMLibDriver.a
lib/libLLVMLineEditor.a
lib/libLLVMLinker.a
lib/libLLVMMC.a
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
lib/libLLVMMCA.a
lib/libLLVMMCDisassembler.a
lib/libLLVMMCJIT.a
lib/libLLVMMCParser.a
lib/libLLVMMIRParser.a
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
${PLIST.MSP430}lib/libLLVMMSP430AsmParser.a
${PLIST.MSP430}lib/libLLVMMSP430AsmPrinter.a
${PLIST.MSP430}lib/libLLVMMSP430CodeGen.a
${PLIST.MSP430}lib/libLLVMMSP430Desc.a
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
${PLIST.MSP430}lib/libLLVMMSP430Disassembler.a
${PLIST.MSP430}lib/libLLVMMSP430Info.a
${PLIST.Mips}lib/libLLVMMipsAsmParser.a
${PLIST.Mips}lib/libLLVMMipsAsmPrinter.a
${PLIST.Mips}lib/libLLVMMipsCodeGen.a
${PLIST.Mips}lib/libLLVMMipsDesc.a
${PLIST.Mips}lib/libLLVMMipsDisassembler.a
${PLIST.Mips}lib/libLLVMMipsInfo.a
${PLIST.NVPTX}lib/libLLVMNVPTXAsmPrinter.a
${PLIST.NVPTX}lib/libLLVMNVPTXCodeGen.a
${PLIST.NVPTX}lib/libLLVMNVPTXDesc.a
${PLIST.NVPTX}lib/libLLVMNVPTXInfo.a
lib/libLLVMObjCARCOpts.a
lib/libLLVMObject.a
lib/libLLVMObjectYAML.a
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
lib/libLLVMOptRemarks.a
lib/libLLVMOption.a
lib/libLLVMOrcJIT.a
lib/libLLVMPasses.a
${PLIST.PowerPC}lib/libLLVMPowerPCAsmParser.a
${PLIST.PowerPC}lib/libLLVMPowerPCAsmPrinter.a
${PLIST.PowerPC}lib/libLLVMPowerPCCodeGen.a
${PLIST.PowerPC}lib/libLLVMPowerPCDesc.a
${PLIST.PowerPC}lib/libLLVMPowerPCDisassembler.a
${PLIST.PowerPC}lib/libLLVMPowerPCInfo.a
lib/libLLVMProfileData.a
lib/libLLVMRuntimeDyld.a
lib/libLLVMScalarOpts.a
lib/libLLVMSelectionDAG.a
${PLIST.Sparc}lib/libLLVMSparcAsmParser.a
${PLIST.Sparc}lib/libLLVMSparcAsmPrinter.a
${PLIST.Sparc}lib/libLLVMSparcCodeGen.a
${PLIST.Sparc}lib/libLLVMSparcDesc.a
${PLIST.Sparc}lib/libLLVMSparcDisassembler.a
${PLIST.Sparc}lib/libLLVMSparcInfo.a
lib/libLLVMSupport.a
lib/libLLVMSymbolize.a
${PLIST.SystemZ}lib/libLLVMSystemZAsmParser.a
${PLIST.SystemZ}lib/libLLVMSystemZAsmPrinter.a
${PLIST.SystemZ}lib/libLLVMSystemZCodeGen.a
${PLIST.SystemZ}lib/libLLVMSystemZDesc.a
${PLIST.SystemZ}lib/libLLVMSystemZDisassembler.a
${PLIST.SystemZ}lib/libLLVMSystemZInfo.a
lib/libLLVMTableGen.a
lib/libLLVMTarget.a
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
lib/libLLVMTextAPI.a
lib/libLLVMTransformUtils.a
lib/libLLVMVectorize.a
2019-06-02 11:48:29 +02:00
${PLIST.WebAssembly}lib/libLLVMWebAssemblyAsmParser.a
${PLIST.WebAssembly}lib/libLLVMWebAssemblyAsmPrinter.a
${PLIST.WebAssembly}lib/libLLVMWebAssemblyCodeGen.a
${PLIST.WebAssembly}lib/libLLVMWebAssemblyDesc.a
${PLIST.WebAssembly}lib/libLLVMWebAssemblyDisassembler.a
${PLIST.WebAssembly}lib/libLLVMWebAssemblyInfo.a
llvm: updated to 6.0.1 6.0.1: Non-comprehensive list of changes in this release Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper. The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use. The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget. The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost. Significantly improved quality of CodeView debug info for Windows. Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer). Changes to the LLVM IR ---------------------- The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort. Changes to the AArch64 Target ----------------------------- Enabled the new GlobalISel instruction selection framework by default at -O0. Changes to the ARM Target ------------------------- Support for enabling SjLj exception handling on platforms where it isn’t the default. Changes to the Hexagon Target ----------------------------- The Hexagon backend now supports V65 ISA. The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version. The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future. The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled. Changes to the MIPS Target -------------------------- Fixed numerous bugs: fpowi on MIPS64 giving incorrect results when used with a negative integer. Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash. Fixed a conversion bug when using the DSP ASE. Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used. Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions. Fixed a crash when using a type of unknown size with gp relative addressing. Corrected the j macro for microMIPS. Corrected the encoding of movep for microMIPS32r6. Fixed an issue with the usage of insert instructions having an invalid set of operands. Fixed an issue where TLS symbols were not marked as such. Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores. Corrected the ELF headers when using the DSP ASE. New features: The long branch pass now generates some R6 specific instructions when targeting MIPSR6. The delay slot filler now performs more branch conversions if delay slots cannot be filled. The MIPS MT ASE is now fully supported. Added support for the lapc pseudo instruction. Improved the selection of multiple instructions (dext, nmadd, nmsub). Further improved microMIPS codesize reduction. Deprecation notices: microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed. Changes to the SystemZ Target ----------------------------- During this release the SystemZ target has: Added support for 128-bit atomic operations. Added support for the “o” constraint for inline asm statements. Changes to the X86 Target ------------------------- During this release the X86 target has: Added support for enabling SjLj exception handling on platforms where it isn’t the default. Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. Added support for Intel Icelake CPU. Fixed some X87 codegen bugs. Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. Improved scheduler model for AMD Jaguar CPUs. Improved llvm-mc’s disassembler for some EVEX encoded instructions. Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. Improved codegen for memory comparisons Improved codegen for i32 vector multiplies Improved codegen for scalar integer absolute values Improved codegen for vector integer rotations (XOP and AVX512) Improved codegen of data being transferred between GPRs and K-registers. Improved codegen for vector truncations. Improved folding of address computations into gather/scatter instructions. Gained initial support recognizing variable shuffles from vector element extracts and inserts. Improved documentation for SSE/AVX intrinsics in intrin.h header files. Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
2018-08-07 12:44:50 +02:00
lib/libLLVMWindowsManifest.a
${PLIST.X86}lib/libLLVMX86AsmParser.a
${PLIST.X86}lib/libLLVMX86AsmPrinter.a
${PLIST.X86}lib/libLLVMX86CodeGen.a
${PLIST.X86}lib/libLLVMX86Desc.a
${PLIST.X86}lib/libLLVMX86Disassembler.a
${PLIST.X86}lib/libLLVMX86Info.a
${PLIST.X86}lib/libLLVMX86Utils.a
${PLIST.XCore}lib/libLLVMXCoreAsmPrinter.a
${PLIST.XCore}lib/libLLVMXCoreCodeGen.a
${PLIST.XCore}lib/libLLVMXCoreDesc.a
${PLIST.XCore}lib/libLLVMXCoreDisassembler.a
${PLIST.XCore}lib/libLLVMXCoreInfo.a
lib/libLLVMXRay.a
lib/libLLVMipo.a
lib/libLTO.${SOEXT}
llvm: updated to 8.0.0 8.0.0: Non-comprehensive list of changes in this release * The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command. * The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass. * For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed. * Added support for labels as offsets in .reloc directive. * Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag. * Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC. * Windows support for libFuzzer (x86_64).
2019-06-02 10:35:55 +02:00
${PLIST.notdylib}lib/libLTO.${SOEXT}.8
${PLIST.notdylib}lib/libOptRemarks.${SOEXT}.8
2019-06-02 11:48:29 +02:00
lib/libOptRemarks.so
llvm: updated to 5.0.0 5.0.0: Non-comprehensive list of changes in this release * LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW. * A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats. * The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents. * The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass. * A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option. * A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap. * A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
2017-12-01 20:22:12 +01:00
share/opt-viewer/opt-diff.py
share/opt-viewer/opt-stats.py
share/opt-viewer/opt-viewer.py
share/opt-viewer/optpmap.py
share/opt-viewer/optrecord.py
share/opt-viewer/style.css