pkgsrc/cad/verilog-current/distinfo

$NetBSD: distinfo,v 1.29 2007/03/01 01:03:45 dmcmahill Exp $

SHA1 (verilog-20070227.tar.gz) = eb6f26393946505617b7a7e2405e760b92eefbf0
RMD160 (verilog-20070227.tar.gz) = c9add1099fb07b50df3a5d232b3307d64bb235c9
Size (verilog-20070227.tar.gz) = 1583940 bytes
SHA1 (patch-ad) = 9492af75153405c49076f2dcd11d2dc338640514
update to verilog-current-20070227 Release Notes for Icarus Verilog Snapshot 20070227 * Fix some problems with specify block parsing. Detect some cases that are parsed but not properly implemented yet and issue warnings or errors. Also fixed a few problems with inertial delay model timing. * Detect is some cases Verilog source errors that can be better reported to users. This includes more specific error messages for certain syntax errors. * Fix problems with overridden continuous assignments. * Hide bool types from logic type as far as VPI is concerned, for the sake of compatibility. * Fix a variety of code generator expression lifetime bugs that caused obscure (and wrong) output results in behavioral code. * iverilog-vpi uses the compiler selected at build time. * Rework handling of strings to handle escape sequences properly. * Fix some handling of real values in some expression types. * Get padding of sized, unsigned numbers when x or z are involved. * Many, many more misc. bug fixes. * Add an assert mechinism that improves usefulness of bug reports by reporting source file line numbers when available. * Compile fixes, using inttypes.h instead of stdint for portability. * Various spelling fixes. 2007-03-01 02:03:45 +01:00			$NetBSD: distinfo,v 1.29 2007/03/01 01:03:45 dmcmahill Exp $
+ move the distfile digest/checksum value from files/md5 to distinfo + move the patch digest/checksum values from files/patch-sum to distinfo 2001-04-17 12:22:24 +02:00
update to verilog-current-20070227 Release Notes for Icarus Verilog Snapshot 20070227 * Fix some problems with specify block parsing. Detect some cases that are parsed but not properly implemented yet and issue warnings or errors. Also fixed a few problems with inertial delay model timing. * Detect is some cases Verilog source errors that can be better reported to users. This includes more specific error messages for certain syntax errors. * Fix problems with overridden continuous assignments. * Hide bool types from logic type as far as VPI is concerned, for the sake of compatibility. * Fix a variety of code generator expression lifetime bugs that caused obscure (and wrong) output results in behavioral code. * iverilog-vpi uses the compiler selected at build time. * Rework handling of strings to handle escape sequences properly. * Fix some handling of real values in some expression types. * Get padding of sized, unsigned numbers when x or z are involved. * Many, many more misc. bug fixes. * Add an assert mechinism that improves usefulness of bug reports by reporting source file line numbers when available. * Compile fixes, using inttypes.h instead of stdint for portability. * Various spelling fixes. 2007-03-01 02:03:45 +01:00			`SHA1 (verilog-20070227.tar.gz) = eb6f26393946505617b7a7e2405e760b92eefbf0`
			`RMD160 (verilog-20070227.tar.gz) = c9add1099fb07b50df3a5d232b3307d64bb235c9`
			`Size (verilog-20070227.tar.gz) = 1583940 bytes`
Update to 20060809 snapshot. There have been several changes since the last packaged snapshot. Those are: -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060215 -------------------------------------------------- * Part select of memory words should now work according to Verilog-2001. This also led to some cleanup of the handling of types internally, as well as some infrastructure for general arrays. * Minor fix to parsing of (* ) attributes. Fix rounding of reals to integers. * Clean up some of the vvp engine related to memories. Remove some dead instructions. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060409 -------------------------------------------------- the most substantial difference in this snapshot the first signs of generate support. The compiler now supports generate loops and has been tested with examples that include wires and gates within the generate scheme. The regression test suite has very few generate tests, so any concise self-testing test programs that use generate would be helpful. Also, instance arrays that use overridden parameters now work properly. Task arguments are a bit more flexible in order to support vendor (notably Xilinx) models that use more interesting task arguments. Runtime support for bi-directional ports had some bugs fixed, along with some other minor run-time bugs. Also, the runtime gains support for typed parameters. And also, there are some new runtime callbacks for events and memories. Parameters had a few types related bugs fixed. They are a bit more flexible now. And various minor compilation errors have been fixed. This includes C/C++ compilation errors fixes, and some configure/Makefile tweaks. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060618 -------------------------------------------------- Add support for system functions in continuous assignments. Allow concatenations as arguments to inout ports. This comes with a small variety of internal part select and concatenation bug fixes. Fix some bugs in constant propagation through ternary expressions. Fix broken subtraction if small constants in certain cases. Fix a few datatype mismatch errors. Make $readmem give warning when input is inadequate for requested range. Fix runtime of nand in continuous assignments. Fix synchronous user defined primiteves to only follow edges. Fix a runtime error in some thread delays processing. Improve limited genvar expression handling. Start a rework of expression elaboration. Make elaboration aware of the expression context width when appropriate in order to better handle expression width and padding. Fix the make rules for parse.cc to reflect that they come from the same source. Fix the autoconf.sh to configure the stub target. Fix portability of the lexor source files on Windows systems. Get rid of the isatty references. Make a stub lround when the system version is missing. -------------------------------------------------- * Release Notes for Snapshot 20060809 -------------------------------------------------- Some handling of real values is improved. Real valued literals are handled in net contexts (continuous assignment, etc.). Also, modulus of real operands now works. (This is an extension to the Verilog standard.) The power operator (**) now works. Signed right shift works properly now. The $sscanf and $fscanf are introduced, and work at least for basic numeric values. The release function now works to undo general force statements, and not just contant force statements. Delay constants up to 64 bits are supported. This at first doesn't seem like an issue, but when precisions are mixed, it becomes surprisingly easy to overflow 32bit delays. The driver is reworked to pass many preprocessor details through a temporary file instead of on the command line of a system(3) call. This prevents confusing and incorrect shell processing of complex strings passed as values to -D flags. Various other little fixes. 2006-08-11 15:28:08 +02:00			`SHA1 (patch-ad) = 9492af75153405c49076f2dcd11d2dc338640514`