2021-10-26 12:04:09 +02:00
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$NetBSD: distinfo,v 1.13 2021/10/26 10:04:15 nia Exp $
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2003-06-05 20:50:54 +02:00
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2021-10-26 12:04:09 +02:00
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BLAKE2s (myhdl-0.10.tar.gz) = b32a10dcfdf4cead07e948d53615655e38bfa20aeaad2ab711e0493851818d21
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Update cad/MyHDL from 0.9.0 to 0.10
pkgsrc packages altered:
- cad/MyHDL-gplcver
- cad/MyHDL-iverilog
- cad/py-MyHDL
upstream changelog
------------------------
What’s new in MyHDL 0.10
The block decorator
Rationale
The historical approach for hierarchy extraction in MyHDL suffers from
significant issues. This results in complex code, a number of non-intuitive API
concepts, and difficulties for future development.
In this release, a new block decorator is introduced to address these issues.
For an in-depth discussion, see mep-114.
API
block() :noindex:
The block decorator enables a method-based API which is more consistent,
simplifies implementation, and reduces the size of the myhdl namespace.
The methods work on block instances, created by calling a function
decorated with the block decorator:
@block
def myblock(<ports>):
...
return <instances>
inst = myblock(<port-associations>)
# inst supports the methods of the block instance API
The API on a block instance looks as follows:
<block_instance>.run_sim(duration=None)
Run a simulation “forever” (default) or for a specified duration.
<block_instance>.config_sim(backend='myhdl', trace=False)
- Optional simulation configuration:
- backend: Defaults to ‘myhdl
- trace: Enable waveform tracing, default False.
<block_instance>.quit_sim()
Quit an active simulation. This is method is currently required because
only a single simulation can be active.
<block_instance>.convert(hdl='Verilog', **kwargs)
- Converts MyHDL code to a target HDL.
- hdl: ‘VHDL’ or ‘Verilog’. Defaults to Verilog.
- Supported keyword arguments:
- path: Destination folder. Defaults to current working dir.
- name: Module and output file name. Defaults to self.mod.__name__.
- trace: Whether the testbench should dump all signal waveforms. Defaults to
False.
- testbench: Verilog only. Specifies whether a testbench should be created.
Defaults to True.
- timescale: timescale parameter. Defaults to ‘1ns/10ps’. Verilog only.
<block_instance>.verify_convert()
Verify conversion output, by comparing target HDL simulation log with MyHDL
simulation log.
<block_instance>.analyze_convert()
Analyze conversion output by compilation with target HDL compiler.
Backwards compatibility issues
In the 0.10 release, the old API still available next to the new API based on
the block decorator.
It is likely that the old API will be deprecated in a future release, resulting
in backwards incompatibility for legacy code. Therefore, users are encouraged
to start using the new API in their development methodology.
2018-04-12 17:08:58 +02:00
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SHA512 (myhdl-0.10.tar.gz) = b250c8b09a2cfbd2a70da60d567c8bcb09747c3e8df536cdd28ad49a8a6fbe5a28395295a6ed6046ced745b617fb3804ceb0f83d9b34db7c70701148ae7db25b
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Size (myhdl-0.10.tar.gz) = 1205466 bytes
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2018-12-27 17:01:54 +01:00
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SHA1 (patch-myhdl___always__seq.py) = 2ba91a28a40f5582a7ab509ee8e619ce92333e92
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SHA1 (patch-myhdl_conversion___toVHDL.py) = 85651035475d908749306dfd57895060582a2051
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