pkgsrc/cad/py-MyHDL/distinfo

$NetBSD: distinfo,v 1.3 2005/02/23 14:59:25 agc Exp $

SHA1 (myhdl-0.4.1.tar.gz) = 84096c83351152b1354a331a0b8c3c1bf4098dde
RMD160 (myhdl-0.4.1.tar.gz) = 237995b0ef44653a43ca478b163a3512f59d5e7c
Size (myhdl-0.4.1.tar.gz) = 1205572 bytes
Add RMD160 digests in addition to SHA1 ones. 2005-02-23 15:59:23 +01:00			$NetBSD: distinfo,v 1.3 2005/02/23 14:59:25 agc Exp $
a library which uses Python as a hardware description language, using the new generator constructs (like pysim, at a first glance) 2003-06-05 20:50:54 +02:00
update to 0.4.1 changes: * VCD output for waveform viewing - function additions - needs Python 2.3, 2.4 is OK * Conversion to Verilog to provide a path to implementation * Added cosimulation support for the cver Verilog simulator. - bugfixes 2005-01-05 16:20:10 +01:00			`SHA1 (myhdl-0.4.1.tar.gz) = 84096c83351152b1354a331a0b8c3c1bf4098dde`
Add RMD160 digests in addition to SHA1 ones. 2005-02-23 15:59:23 +01:00			`RMD160 (myhdl-0.4.1.tar.gz) = 237995b0ef44653a43ca478b163a3512f59d5e7c`
update to 0.4.1 changes: * VCD output for waveform viewing - function additions - needs Python 2.3, 2.4 is OK * Conversion to Verilog to provide a path to implementation * Added cosimulation support for the cver Verilog simulator. - bugfixes 2005-01-05 16:20:10 +01:00			`Size (myhdl-0.4.1.tar.gz) = 1205572 bytes`