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pkgsrc/cad/py-MyHDL/PLIST

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update to 0.4.1 changes: * VCD output for waveform viewing - function additions - needs Python 2.3, 2.4 is OK * Conversion to Verilog to provide a path to implementation * Added cosimulation support for the cver Verilog simulator. - bugfixes
2005-01-05 16:20:10 +01:00
@comment $NetBSD: PLIST,v 1.3 2005/01/05 15:20:10 drochner Exp $
${PYSITELIB}/myhdl/_Cosimulation.py
${PYSITELIB}/myhdl/_Cosimulation.pyc
${PYSITELIB}/myhdl/_Cosimulation.pyo
${PYSITELIB}/myhdl/_Signal.py
${PYSITELIB}/myhdl/_Signal.pyc
${PYSITELIB}/myhdl/_Signal.pyo
${PYSITELIB}/myhdl/_Simulation.py
${PYSITELIB}/myhdl/_Simulation.pyc
${PYSITELIB}/myhdl/_Simulation.pyo
${PYSITELIB}/myhdl/_Waiter.py
${PYSITELIB}/myhdl/_Waiter.pyc
${PYSITELIB}/myhdl/_Waiter.pyo
a library which uses Python as a hardware description language, using the new generator constructs (like pysim, at a first glance)
2003-06-05 20:50:54 +02:00
${PYSITELIB}/myhdl/__init__.py
${PYSITELIB}/myhdl/__init__.pyc
hange extension.mk to also install optimized files for distutils packages. Inspired by FreeBSD "ports". Fix the PLISTs accordingly. Also, while at it, remove now obsolete compileall.py calls in post-install targets and insure that extension.mk is in included before builinlinks of other Python modules. Discussed with/ok'ed by drochner@.
2003-09-14 18:43:45 +02:00
${PYSITELIB}/myhdl/__init__.pyo
update to 0.4.1 changes: * VCD output for waveform viewing - function additions - needs Python 2.3, 2.4 is OK * Conversion to Verilog to provide a path to implementation * Added cosimulation support for the cver Verilog simulator. - bugfixes
2005-01-05 16:20:10 +01:00
${PYSITELIB}/myhdl/_always_comb.py
${PYSITELIB}/myhdl/_always_comb.pyc
${PYSITELIB}/myhdl/_always_comb.pyo
${PYSITELIB}/myhdl/_bin.py
${PYSITELIB}/myhdl/_bin.pyc
${PYSITELIB}/myhdl/_bin.pyo
${PYSITELIB}/myhdl/_cell_deref.py
${PYSITELIB}/myhdl/_cell_deref.pyc
${PYSITELIB}/myhdl/_cell_deref.pyo
${PYSITELIB}/myhdl/_concat.py
${PYSITELIB}/myhdl/_concat.pyc
${PYSITELIB}/myhdl/_concat.pyo
${PYSITELIB}/myhdl/_delay.py
${PYSITELIB}/myhdl/_delay.pyc
${PYSITELIB}/myhdl/_delay.pyo
${PYSITELIB}/myhdl/_enum.py
${PYSITELIB}/myhdl/_enum.pyc
${PYSITELIB}/myhdl/_enum.pyo
${PYSITELIB}/myhdl/_extractHierarchy.py
${PYSITELIB}/myhdl/_extractHierarchy.pyc
${PYSITELIB}/myhdl/_extractHierarchy.pyo
${PYSITELIB}/myhdl/_intbv.py
${PYSITELIB}/myhdl/_intbv.pyc
${PYSITELIB}/myhdl/_intbv.pyo
${PYSITELIB}/myhdl/_isGenSeq.py
${PYSITELIB}/myhdl/_isGenSeq.pyc
${PYSITELIB}/myhdl/_isGenSeq.pyo
${PYSITELIB}/myhdl/_join.py
${PYSITELIB}/myhdl/_join.pyc
${PYSITELIB}/myhdl/_join.pyo
${PYSITELIB}/myhdl/_misc.py
${PYSITELIB}/myhdl/_misc.pyc
${PYSITELIB}/myhdl/_misc.pyo
a library which uses Python as a hardware description language, using the new generator constructs (like pysim, at a first glance)
2003-06-05 20:50:54 +02:00
${PYSITELIB}/myhdl/_simulator.py
${PYSITELIB}/myhdl/_simulator.pyc
hange extension.mk to also install optimized files for distutils packages. Inspired by FreeBSD "ports". Fix the PLISTs accordingly. Also, while at it, remove now obsolete compileall.py calls in post-install targets and insure that extension.mk is in included before builinlinks of other Python modules. Discussed with/ok'ed by drochner@.
2003-09-14 18:43:45 +02:00
${PYSITELIB}/myhdl/_simulator.pyo
update to 0.4.1 changes: * VCD output for waveform viewing - function additions - needs Python 2.3, 2.4 is OK * Conversion to Verilog to provide a path to implementation * Added cosimulation support for the cver Verilog simulator. - bugfixes
2005-01-05 16:20:10 +01:00
${PYSITELIB}/myhdl/_toVerilog/__init__.py
${PYSITELIB}/myhdl/_toVerilog/__init__.pyc
${PYSITELIB}/myhdl/_toVerilog/__init__.pyo
${PYSITELIB}/myhdl/_toVerilog/_analyze.py
${PYSITELIB}/myhdl/_toVerilog/_analyze.pyc
${PYSITELIB}/myhdl/_toVerilog/_analyze.pyo
${PYSITELIB}/myhdl/_toVerilog/_convert.py
${PYSITELIB}/myhdl/_toVerilog/_convert.pyc
${PYSITELIB}/myhdl/_toVerilog/_convert.pyo
${PYSITELIB}/myhdl/_traceSignals.py
${PYSITELIB}/myhdl/_traceSignals.pyc
${PYSITELIB}/myhdl/_traceSignals.pyo
${PYSITELIB}/myhdl/_unparse.py
${PYSITELIB}/myhdl/_unparse.pyc
${PYSITELIB}/myhdl/_unparse.pyo
${PYSITELIB}/myhdl/_util.py
${PYSITELIB}/myhdl/_util.pyc
${PYSITELIB}/myhdl/_util.pyo
@dirrm ${PYSITELIB}/myhdl/_toVerilog
a library which uses Python as a hardware description language, using the new generator constructs (like pysim, at a first glance)
2003-06-05 20:50:54 +02:00
@dirrm ${PYSITELIB}/myhdl
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