5 lines
224 B
Text
5 lines
224 B
Text
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Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also
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implements some of the 2001 P1364 standard features. All three
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PLI interfaces (tf_, acc_, and vpi_) are implemented as defined
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in the IEEE 2001 P1364 LRM.
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