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update to verilog-0.8.3 ** Release Notes for Icarus Verilog 0.8.3 This is a new release of the stable 0.8 branch. The changes from 0.8.2 are intended to be evolutionary, rather then revolutionary, to enhance the stability of the branch. Various simulator bugs have been fixed, including (but not limited to): - Detect overrun of timescale vs. precision - Handle more operators in constant expressions - Various ivl crashes and panics fixed. - Some performance bottlenecks have been fixed. - Various tool compilation problems have been fixed. Also, the internal synthesizer (for synthesis targets) has been considerably improved. NOTE that the code generators have not been improved to take advantage of all the changes here, so there is work yet to be done. The mingw build process for compiling in Windows has been reworked. It is now possible (indeed preferable) to compile fully native Icarus Verilog binaries on Windows with no Cygwin tools at all.
2006-10-05 01:52:47 +02:00
# $NetBSD: Makefile,v 1.30 2006/10/04 23:52:47 dmcmahill Exp $
Initial import of Icarus Verilog. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.
2000-01-26 16:28:40 +01:00
#
update to verilog-0.8.3 ** Release Notes for Icarus Verilog 0.8.3 This is a new release of the stable 0.8 branch. The changes from 0.8.2 are intended to be evolutionary, rather then revolutionary, to enhance the stability of the branch. Various simulator bugs have been fixed, including (but not limited to): - Detect overrun of timescale vs. precision - Handle more operators in constant expressions - Various ivl crashes and panics fixed. - Some performance bottlenecks have been fixed. - Various tool compilation problems have been fixed. Also, the internal synthesizer (for synthesis targets) has been considerably improved. NOTE that the code generators have not been improved to take advantage of all the changes here, so there is work yet to be done. The mingw build process for compiling in Windows has been reworked. It is now possible (indeed preferable) to compile fully native Icarus Verilog binaries on Windows with no Cygwin tools at all.
2006-10-05 01:52:47 +02:00
DISTNAME= verilog-0.8.3
update to verilog-0.4. from the authors announcement: So many things have changed since version 0.3 that there is no point in listing them. There have been tons and tons of bug fixes and the language coverage is better, and so on and so forth. It's just so very much better then version 0.3:-) speaking as a user, some of my personal favorites are: - support for signed variables - iverilog now gives correct return codes (which makes 'make' much happier) for a more complete list, the commit messages for pkgsrc/cad/verilog-current/Makefile contain the changes for each development snapshot between verilog-0.3 and verilog-0.4
2001-02-04 16:36:49 +01:00
CATEGORIES= cad
update to verilog-0.8. The current release is a considerable improvement over the previous stable release. It includes 20 months of fixes and language coverage improvements. For a complete history of changes, see the release notes for individual snapshots between the 0.7 and 0.8 releases found at ftp://ftp.icarus.com/pub/eda/verilog/snapshots/pre-0.8 A brief list of highlights: - Support for advanced standard data types such as real, - Lots more language support in general, - Kernel of an extensible, interactive debugger is new, - More complete support for user supplied system functions and tasks, including PLI system functions with various return value types, - Better standards compliance for core system tasks and functions in general, including some Verilog 2001 file I/O support, and - Performance improvements in general.
2004-10-15 00:29:04 +02:00
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.8/
Initial import of Icarus Verilog. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.
2000-01-26 16:28:40 +01:00
s/netbsd.org/NetBSD.org/
2003-07-17 23:21:03 +02:00
MAINTAINER= dmcmahill@NetBSD.org
update to verilog-0.4. from the authors announcement: So many things have changed since version 0.3 that there is no point in listing them. There have been tons and tons of bug fixes and the language coverage is better, and so on and so forth. It's just so very much better then version 0.3:-) speaking as a user, some of my personal favorites are: - support for signed variables - iverilog now gives correct return codes (which makes 'make' much happier) for a more complete list, the commit messages for pkgsrc/cad/verilog-current/Makefile contain the changes for each development snapshot between verilog-0.3 and verilog-0.4
2001-02-04 16:36:49 +01:00
HOMEPAGE= http://icarus.com/eda/verilog/index.html
Update to new COMMENT style: COMMENT var in Makefile instead of pkg/COMMENT.
2001-02-16 14:41:26 +01:00
COMMENT= Verilog simulation and synthesis tool (stable release version)
Initial import of Icarus Verilog. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.
2000-01-26 16:28:40 +01:00
bl3ify
2004-03-12 03:51:53 +01:00
PKG_INSTALLATION_TYPES= overwrite pkgviews
Use wildcards in CONFLICTS.
2001-04-11 15:36:19 +02:00
CONFLICTS+= verilog-current-[0-9]*
Update to the released version 0.2 of verilog. I will be creating a seperate verilog-current pkg to track development snapshots. This version has minor bug fixes over the previous snapshot package. Notable $display of a memory element now works correctly and a bug in $readmemb has been fixed.
2000-03-07 17:05:13 +01:00
add missing USE_LANGUAGES
2006-01-29 14:56:29 +01:00
USE_LANGUAGES= c c++
Replace explicit build dependencies on bison and manipulations on the YACC variable with USE_TOOLS+=bison.
2005-05-22 22:28:47 +02:00
GNU_CONFIGURE= yes
For building verilog, lex is indeed needed.
2006-05-28 19:31:26 +02:00
USE_TOOLS+= gmake bison lex
update to verilog-0.5 * The Big Change: VVP Past versions of Icarus Verilog performed simulation by compiling the Verilog design to intermediate C++ code, then in turn compiling that C++ (usually with G++) to a binary executable. This program was then executed to actually run the simulation. The 0.5 compiler, however, uses a custom internal language called "vvp." The vvp code generator writes a program in the vvp language that the vvp interpreter executes. This gets runtime performance similar to the older vvm method, but compile times are much faster. The result of this change is that there is a new program, ``vvp'', that is installed with the existing ``iverilog'' compiler. This program actually executes the simulation generated by the vvp code generator. There are manual pages for the iverilog command and the new vvp command, as well as a QUICK_START document to help you run your first simulation. * What Else Is New The compiler itself is now a lot more robust. While it still does not compile and understand the entire IEEE1364 standard, the compiler is less likely to crash on bad input, gives better error messages, and has generally been cleaned up.
2001-08-04 03:20:43 +02:00
CONFIGURE_ARGS+= --without-ipal
Replace explicit build dependencies on bison and manipulations on the YACC variable with USE_TOOLS+=bison.
2005-05-22 22:28:47 +02:00
TEST_TARGET= check
Initial import of Icarus Verilog. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.
2000-01-26 16:28:40 +01:00
update to verilog-0.8. The current release is a considerable improvement over the previous stable release. It includes 20 months of fixes and language coverage improvements. For a complete history of changes, see the release notes for individual snapshots between the 0.7 and 0.8 releases found at ftp://ftp.icarus.com/pub/eda/verilog/snapshots/pre-0.8 A brief list of highlights: - Support for advanced standard data types such as real, - Lots more language support in general, - Kernel of an extensible, interactive debugger is new, - More complete support for user supplied system functions and tasks, including PLI system functions with various return value types, - Better standards compliance for core system tasks and functions in general, including some Verilog 2001 file I/O support, and - Performance improvements in general.
2004-10-15 00:29:04 +02:00
.include "../../devel/zlib/buildlink3.mk"
.include "../../archivers/bzip2/buildlink3.mk"
.include "../../devel/gperf/buildlink3.mk"
.include "../../devel/readline/buildlink3.mk"
Initial import of Icarus Verilog. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.
2000-01-26 16:28:40 +01:00
.include "../../mk/bsd.pkg.mk"
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