pkgsrc/cad/verilog-current/distinfo

$NetBSD: distinfo,v 1.25 2006/01/25 12:11:01 dmcmahill Exp $

SHA1 (verilog-20060124.tar.gz) = 4b3784aeb5b91c0672522cd420dd96e73bd4e33c
RMD160 (verilog-20060124.tar.gz) = de536f3d9c811dbbeea36bb64007aa26355dddcb
Size (verilog-20060124.tar.gz) = 1507887 bytes
SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a
update to 20060124 snapshot. A few new features have been added to allow proper simulation with newer Xilinx UNISIM models. (They are starting to use Verilog 2001 features.) And also various bug fixes in this release. -- Primitive and continuous assign delays can now be non-constant. This needed some new run-time support, so vvp had a slight format change, and certain new optimizations follow as a result. -- Bug handling certain constant sub-expressions in concatenation expressions. Also, allow concat expressions in constant contexts. -- Support for wide divide expressions. -- Fixes for stubborn compilers. -- Fix bugs in padding of signed expressions. -- More fixes for following the data types of expressions. 2006-01-25 13:11:00 +01:00			$NetBSD: distinfo,v 1.25 2006/01/25 12:11:01 dmcmahill Exp $
+ move the distfile digest/checksum value from files/md5 to distinfo + move the patch digest/checksum values from files/patch-sum to distinfo 2001-04-17 12:22:24 +02:00
update to 20060124 snapshot. A few new features have been added to allow proper simulation with newer Xilinx UNISIM models. (They are starting to use Verilog 2001 features.) And also various bug fixes in this release. -- Primitive and continuous assign delays can now be non-constant. This needed some new run-time support, so vvp had a slight format change, and certain new optimizations follow as a result. -- Bug handling certain constant sub-expressions in concatenation expressions. Also, allow concat expressions in constant contexts. -- Support for wide divide expressions. -- Fixes for stubborn compilers. -- Fix bugs in padding of signed expressions. -- More fixes for following the data types of expressions. 2006-01-25 13:11:00 +01:00			`SHA1 (verilog-20060124.tar.gz) = 4b3784aeb5b91c0672522cd420dd96e73bd4e33c`
			`RMD160 (verilog-20060124.tar.gz) = de536f3d9c811dbbeea36bb64007aa26355dddcb`
			`Size (verilog-20060124.tar.gz) = 1507887 bytes`
update to snapshot "20030705". There was a couple of snapshots since february; besides bugfixes the major highligths might be: -handling of real values at various places -support for library modules (esp cadence PLI1) -better FPGA support (esp Virtex II) -"vvp" interactive mode added Also converted to buildlink2, and dependencies to libz, libbz2 and readline added. 2003-07-14 11:51:48 +02:00			`SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a`