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Enable verilator

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This commit is contained in:
ryoon 2018-12-16 09:39:22 +00:00
parent 42337d01da
commit 0093fdc71d
1 changed files with 2 additions and 1 deletions
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cad/Makefile
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@ -1,4 +1,4 @@
# $NetBSD: Makefile,v 1.96 2018/03/17 22:20:13 mef Exp $
# $NetBSD: Makefile,v 1.97 2018/12/16 09:39:22 ryoon Exp $
#
COMMENT= CAD tools
@ -65,6 +65,7 @@ SUBDIR+= stdio-wcalc
SUBDIR+= tkgate
SUBDIR+= tnt-mmtl
SUBDIR+= transcalc
SUBDIR+= verilator
SUBDIR+= verilog-mode
SUBDIR+= veriwell
SUBDIR+= wcalc