Initial import of verilog-current. This pkg is for the development snapshots

of the cad/verilog package.  Development snapshots are created quite frequently
in between stable releases.

cad/verilog-current/Makefile

@@ -0,0 +1,19 @@
+# $NetBSD: Makefile,v 1.1.1.1 2000/03/07 16:09:15 dmcmahill Exp $
+#
+
+DISTNAME=	verilog-20000219
+PKGNAME=	verilog-current-20000219
+CATEGORIES=	cad
+MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/
+
+MAINTAINER=	dmcmahill@netbsd.org
+HOMEPAGE=	http://icarus.com/eda/verilog/index.html
+
+BUILD_DEPENDS+=	bison:../../devel/bison
+
+CONFLICTS+=	verilog
+
+GNU_CONFIGURE=	YES
+USE_GMAKE=      yes
+
+.include "../../mk/bsd.pkg.mk"

cad/verilog-current/files/md5

@@ -0,0 +1,3 @@
+$NetBSD: md5,v 1.1.1.1 2000/03/07 16:09:15 dmcmahill Exp $
+
+MD5 (verilog-20000219.tar.gz) = 843630e022912cecf80e198308cf4624

cad/verilog-current/files/patch-sum

@@ -0,0 +1,4 @@
+$NetBSD: patch-sum,v 1.1.1.1 2000/03/07 16:09:15 dmcmahill Exp $
+
+MD5 (patch-ad) = 7a12b669a87ec1639958bfc7677e218d
+MD5 (patch-ae) = 44921f529c17458cd3ba34d35dc0da77

cad/verilog-current/patches/patch-ad

@@ -0,0 +1,13 @@
+$NetBSD: patch-ad,v 1.1.1.1 2000/03/07 16:09:16 dmcmahill Exp $
+
+don't use -O2 on parse.cc because of compiler bugs on sparc and pmax
+(maybe others).
+
+--- Makefile.in.orig	Sat Feb  5 01:40:35 2000
++++ Makefile.in	Sun Feb 13 11:13:10 2000
+@@ -111,4 +111,5 @@
+ 
+ parse.o dep/parse.d: parse.cc
++	$(CXX) -c -I. $(CPPFLAGS)  $<
+ 
+ parse.h parse.cc: $(srcdir)/parse.y

cad/verilog-current/patches/patch-ae

@@ -0,0 +1,13 @@
+$NetBSD: patch-ae,v 1.1.1.1 2000/03/07 16:09:16 dmcmahill Exp $
+
+use the correct flag for our compiler.
+
+--- verilog.sh.orig	Sat Feb  5 01:40:35 2000
++++ verilog.sh	Sun Feb 13 11:15:00 2000
+@@ -117,5 +117,5 @@
+     "xnf") mv ${tmpCCFile} ${outputFile} ;;
+ 
+-    "vvm")  ${execCpp} -rdynamic -I${includedir} -L${libdir} ${tmpCCFile} -o ${outputFile} -lvvm @dllib@ ;
++    "vvm")  ${execCpp} -Wl,--export-dynamic -I${includedir} -L${libdir} ${tmpCCFile} -o ${outputFile} -lvvm @dllib@ ;
+ 	    if test $? -ne 0 ; then
+ 	     echo "C++ compilation failed. Terminating compilation."

cad/verilog-current/pkg/COMMENT

@@ -0,0 +1 @@
+Verilog simulation and synthesis tool

cad/verilog-current/pkg/DESCR

@@ -0,0 +1,12 @@
+Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a 
+compiler, compiling source code writen in Verilog (IEEE-1364) into some target
+format. For batch simulation, the compiler can generate C++ code that is
+compiled and linked with a run time library (called "vvm") then executed as
+a command to run the simulation. For synthesis, the compiler generates
+netlists in the desired format.
+   
+The compiler proper is intended to parse and elaborate design descriptions
+written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
+complex standard, so it will take some time for it to get there, but that's
+the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
+and some -1999 features will creep in.

cad/verilog-current/pkg/PLIST

@@ -0,0 +1,16 @@
+@comment $NetBSD: PLIST,v 1.1.1.1 2000/03/07 16:09:16 dmcmahill Exp $
+bin/verilog
+bin/gverilog
+include/vpi_user.h
+include/vvm.h
+include/vpi_priv.h
+include/vvm_func.h
+include/vvm_gates.h
+include/vvm_thread.h
+include/vvm_calltf.h
+lib/ivl/ivl
+lib/ivl/system.vpi
+lib/ivl/ivlpp
+lib/libvvm.a
+man/man1/verilog.1
+@dirrm lib/ivl