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Fix cats interrupt issue, cosmetic addition to footbridge.

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This commit is contained in:
christos 2017-05-15 01:45:49 +00:00
parent 9eba1be86f
commit bf71d48719
3 changed files with 63 additions and 3 deletions
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4
emulators/gxemul/Makefile
View file

@ -1,7 +1,7 @@
# $NetBSD: Makefile,v 1.55 2017/05/11 12:38:53 christos Exp $
# $NetBSD: Makefile,v 1.56 2017/05/15 01:45:49 christos Exp $
DISTNAME= gxemul-0.6.0.1
PKGREVISION= 2
PKGREVISION= 3
CATEGORIES= emulators
MASTER_SITES= http://gxemul.sourceforge.net/src/

3
emulators/gxemul/distinfo
View file

@ -1,4 +1,4 @@
$NetBSD: distinfo,v 1.45 2017/05/11 12:38:53 christos Exp $
$NetBSD: distinfo,v 1.46 2017/05/15 01:45:49 christos Exp $
SHA1 (gxemul-0.6.0.1.tar.gz) = 8a9b7a6c08628c2a59a6e7e9c7c449c3826b4744
RMD160 (gxemul-0.6.0.1.tar.gz) = 6943173d4149bfe40218715b8ed2c82b5b361e50
@ -13,6 +13,7 @@ SHA1 (patch-src_components_cpu_M88K__CPUComponent.cc) = 931cdc9a806e9ff48dccb2a6
SHA1 (patch-src_components_cpu_MIPS__CPUComponent.cc) = 75d8276092fcdc9f548f874e5807ae8e6a2b9eae
SHA1 (patch-src_cpus_cpu_mips.cc) = d239116e4ce5e040a1bdf39b803ca9a05500be53
SHA1 (patch-src_cpus_cpu_mips_instr.cc) = be40f86a103d2366d13a884d957848d4f680dc61
SHA1 (patch-src_devices_dev__footbridge.cc) = 2dc76e65fff7e6c846d9d06b74bed76075b0c79a
SHA1 (patch-src_include_components_CPUDyntransComponent.h) = 4fa3c327c4ce5ee9e39e7bc49ce6029b2a7da100
SHA1 (patch-src_include_components_M88K__CPUComponent.h) = afd07ae4df33d0c0a9d3d8c15dca4ef9ee7dd916
SHA1 (patch-src_include_components_MIPS__CPUComponent.h) = 4e49da9af0d220a1ea7c4520d8e7e53d8d84c155

59
emulators/gxemul/patches/patch-src_devices_dev__footbridge.cc Normal file
View file

@ -0,0 +1,59 @@
$NetBSD: patch-src_devices_dev__footbridge.cc,v 1.1 2017/05/15 01:45:49 christos Exp $
- fix hang interrupt issue. Always assert the irq's even if we have alread
asserted the global irq for the device. prevents hangs with cats.
- add cosmetic (no/op) code for the SDRAM setup that cats does.
--- src/devices/dev_footbridge.cc.orig 2014-08-17 04:45:12.000000000 -0400
+++ src/devices/dev_footbridge.cc 2017-05-14 21:30:25.392564100 -0400
@@ -154,7 +154,7 @@
struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
d->irq_status |= interrupt->line;
- if ((d->irq_status & d->irq_enable) && !d->irq_asserted) {
+ if ((d->irq_status & d->irq_enable) /* && !d->irq_asserted */) {
d->irq_asserted = 1;
INTERRUPT_ASSERT(d->irq);
}
@@ -455,6 +455,42 @@
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
break;
+ case SDRAM_BA_MASK:
+ if (writeflag == MEM_READ) {
+ fatal("[ footbridge read to sdram_ba_mask ]\n");
+ exit(1);
+ } else {
+ switch (idata) {
+ case SDRAM_MASK_256KB:
+ case SDRAM_MASK_512KB:
+ case SDRAM_MASK_1MB:
+ case SDRAM_MASK_2MB:
+ case SDRAM_MASK_4MB:
+ case SDRAM_MASK_8MB:
+ case SDRAM_MASK_16MB:
+ case SDRAM_MASK_32MB:
+ case SDRAM_MASK_64MB:
+ case SDRAM_MASK_128MB:
+ case SDRAM_MASK_256MB:
+ break;
+ default:
+ fatal("[ footbridge write to sdram_ba_mask "
+ "%#llx ]\n", (long long)idata);
+ break;
+ }
+ }
+ break;
+ case SDRAM_BA_OFFSET:
+ if (writeflag == MEM_READ) {
+ fatal("[ footbridge read to sdram_ba_offset ]\n");
+ exit(1);
+ } else {
+ if (idata != 0)
+ fatal("[ footbridge write to sdram_ba_offset "
+ "%#llx ]\n", (long long)idata);
+ }
+ break;
+
default:if (writeflag == MEM_READ) {
fatal("[ footbridge: read from 0x%x ]\n",
(int)relative_addr);