import MyHDL-iverilog-0.5, an Icarus Verilog vpi module to support cosimulation

from py-MyHDL

cad/MyHDL-iverilog/DESCR

@@ -0,0 +1,7 @@
+MyHDL is a Python package for using Python as a hardware
+description language. Popular hardware description languages, like
+Verilog and VHDL, are compiled languages. MyHDL with Python
+can be viewed as a "scripting language" counterpart of such
+languages. However, Python is more accurately described as a very
+high level language (VHLL). MyHDL users have access to the
+amazing power and elegance of Python for their modeling work.

cad/MyHDL-iverilog/Makefile

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+# $NetBSD: Makefile,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+#
+
+DISTNAME=	myhdl-0.5
+PKGNAME=	MyHDL-iverilog-0.5
+CATEGORIES=	cad python
+MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
+
+MAINTAINER=	tech-pkg@NetBSD.org
+HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
+COMMENT=	Icarus Verilog cosimulation support for py-MyHDL
+
+BUILD_DIRS+=	cosimulation/icarus
+
+do-install:
+	${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \
+		${PREFIX}/lib/ivl
+
+.include "../../cad/verilog/buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"

cad/MyHDL-iverilog/PLIST

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+@comment $NetBSD: PLIST,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+lib/ivl/myhdl.vpi

cad/MyHDL-iverilog/distinfo

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+$NetBSD: distinfo,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+
+SHA1 (myhdl-0.5.tar.gz) = c97517d7b70d6e4a56f6a2576baa685d53c394d3
+RMD160 (myhdl-0.5.tar.gz) = 2cbc89c5c2bd61a636b64bf5654471900f940ffc
+Size (myhdl-0.5.tar.gz) = 759071 bytes