Release Notes for Icarus Verilog 0.8.7
none (but see below for other releases since the last version in pkgsrc)
Release Notes for Icarus Verilog 0.8.6
This is a bug fix update of the 0.8 stable version of Icarus
Verilog. The v0.8 series tries to remain as stable as possible while
still fixing bugs that are safe to fix.
Preprocessor:
* Fix parse/preprocess of C-style comments in surpressed ifdef
blocks.
* Support leading underscore in preprocessor names.
Compilation/elaboration issues:
* Support min:typ:max expressions in more places.
* Fix handling of @* non-input nets.
* Do not support system functions in continuous assignments.
* Do not support converting vectors to real.
* Do not support constant real valued expressions.
Run-time ussues:
* Fix comparison of negative numbers that happen to be equal.
* Fix bad execution of certain expressions caused by code generator
bad lookaside handling.
* Proper error message for invalid bit selects.
* Implement $printtimescale system task.
Compiler build issues:
* Compile OK evel if libbzip2 is not installed, but do not support
LXT2 in that case.
Release Notes for Icarus Verilog 0.8.5
This is mostly a bug-fix release for the 0.8 stable branch.
* Fix assertions from unary operators with certain operand widths.
* Fix incorrect comparison results when in certain cases comparing two
signed negative integers.
* Latch synthesis has been added to the core synthesizer
* Add nand gate support to the edif code generator
* Minor compile time errors/warnings
* Improved messages from the configure script
Release Notes for Icarus Verilog 0.8.4
This is a bug-fix release for the 0.8 stable branch. The 0.8 stable
branch updates do not include significant new features (they go into
the devel branch instead) nor fixes that are deemed to drastic to
include in a stable tool.
- Various source code portability problems have been fixed. The 0.8 no
longer compiles on many modern systems.
- Various bug reports have been put to rest with this release. Some
parser errors have been fixed (including a few regressions from
0.8.3) and a few new syntaxes added.
- A variety of systhesis bug fixes and enhancements are included in
0.8.4. Currently, synthesis is only actively supported in the 0.8
branch, and the 0.8.4 is the most complete.
** Release Notes for Icarus Verilog 0.8.3
This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.
Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.
Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.
The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.
The current release is a considerable improvement over the previous stable
release. It includes 20 months of fixes and language coverage improvements.
For a complete history of changes, see the release notes for individual
snapshots between the 0.7 and 0.8 releases found at
ftp://ftp.icarus.com/pub/eda/verilog/snapshots/pre-0.8
A brief list of highlights:
- Support for advanced standard data types such as real,
- Lots more language support in general,
- Kernel of an extensible, interactive debugger is new,
- More complete support for user supplied system functions and tasks,
including PLI system functions with various return value types,
- Better standards compliance for core system tasks and functions in
general, including some Verilog 2001 file I/O support, and
- Performance improvements in general.
This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
WHAT'S NEW SINCE 0.5?
Quite a lot. Innumerable bugs have been fixed, and standards coverage
has been improved significantly. Warning and error messages have been
improved, and so has compile performance. Gate delays, strength
modeling, and floating point delays have all improved since the 0.5
release. If you had trouble with the 0.5 release, the 0.6 release
probably fixes your problem.
Support for large designs spanning multiple files has been improved
dramatically. The usual preprocessor inclusion method still works, but
The 0.6 release adds command files for keeping source file lists, and
automatic library searches for missing modules. The library mechinisms
are compatible with commercial tools, and commercial module libraries
can be used with Icarus Verilog.
Many compiler limitations related to the size and complexity of large
designs have been relaxed or eliminated. There are no known design
size limitations remaining in the compiler. Icarus Verilog should be
able to handle any design that you have the patience to compile.
foo-* to foo-[0-9]*. This is to cause the dependencies to match only the
packages whose base package name is "foo", and not those named "foo-bar".
A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net. Also
change dependency examples in Packages.txt to reflect this.
* The Big Change: VVP
Past versions of Icarus Verilog performed simulation by compiling the
Verilog design to intermediate C++ code, then in turn compiling that
C++ (usually with G++) to a binary executable. This program was then
executed to actually run the simulation.
The 0.5 compiler, however, uses a custom internal language called
"vvp." The vvp code generator writes a program in the vvp language
that the vvp interpreter executes. This gets runtime performance
similar to the older vvm method, but compile times are much faster.
The result of this change is that there is a new program, ``vvp'',
that is installed with the existing ``iverilog'' compiler. This
program actually executes the simulation generated by the vvp code
generator.
There are manual pages for the iverilog command and the new vvp
command, as well as a QUICK_START document to help you run your first
simulation.
* What Else Is New
The compiler itself is now a lot more robust. While it still does not
compile and understand the entire IEEE1364 standard, the compiler is
less likely to crash on bad input, gives better error messages, and
has generally been cleaned up.
first component is now a package name+version/pattern, no more
executable/patchname/whatnot.
While there, introduce BUILD_USES_MSGFMT as shorthand to pull in
devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current).
Patch by Alistair Crooks <agc@netbsd.org>
from the authors announcement:
So many things have changed since version 0.3 that there is no point
in listing them. There have been tons and tons of bug fixes and the
language coverage is better, and so on and so forth. It's just so very
much better then version 0.3:-)
speaking as a user, some of my personal favorites are:
- support for signed variables
- iverilog now gives correct return codes (which makes 'make' much happier)
for a more complete list, the commit messages for
pkgsrc/cad/verilog-current/Makefile contain the changes for each
development snapshot between verilog-0.3 and verilog-0.4
Changes, from the authors release statement, are:
This release is a significant improvement over previous releases of
Icarus Verilog, including better language coverage, improved
synthesis, and increased performance.
This release adds to the 0.2 release support for Verilog-2000 style
parameters and parameter overrides, defparam, and localparam,
including proper handling of scoping rules. Also, strength modeling is
added, with support for strengths attached to gates and continuous
assignments.
Combinational user defined primitives have been added to complement
synchronous primitives that were already supported. Support for
primitives should now be fairly complete.
Force/release/assign/deassign syntax now works properly, allowing for
more sophisticated test bench design and debugging.
Bug fixes have been numerous and varied. This release of Icarus
Verilog is considerably more robust then previous versions, thanks to
diligent testing and bug reporting by users all over the world.
verilog-current pkg to track development snapshots.
This version has minor bug fixes over the previous snapshot package. Notable
$display of a memory element now works correctly and a bug in $readmemb has
been fixed.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.
